NSBMC290VF NSC [National Semiconductor], NSBMC290VF Datasheet

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NSBMC290VF

Manufacturer Part Number
NSBMC290VF
Description
Burst Mode Memory Controller
Manufacturer
NSC [National Semiconductor]
Datasheet
C 1995 National Semiconductor Corporation
NSBMC290
Burst Mode Memory Controller
General Description
The
V29BMC
ler is a single chip device designed to simplify the imple-
mentation of burst mode access in high performance sys-
tems using the Am29000
sor
The extremely high instruction rate achieved by this proces-
sor places extraordinary demands on memory system de-
signs if maximum throughput is to be sustained and costs
minimized
The most obvious solution to the problem of access speed
is to implement system memory using high-speed static
memories However the high cost and low density of these
devices make them an expensive and space consumptive
solution
A more cost effective method of solving this problem is via
the use of dynamic RAMs Their high density and low cost
make their use extremely attractive The impediment to their
use is their relatively slow access times
However when operated in page mode dynamic RAMs be-
have more like static memories Properly managed they
can yield access times approaching those of fully static
RAMs
Block Diagram
This document contains information concerning a product that has been developed by National Semiconductor Corporation V3 Corporation This information
is intended to help in evaluating this product National Semiconductor Corporation V3 Corporation reserves the right to change and improve the specifications
of this product without notice
TRI-STATE is a registered trademark National Semiconductor Corporation
NSBMC290
V29BMC
Am29000
TM
TM
NSBMC290
TM
is a trademark of V3 Corporation
is a trademark of Advanced Micro Devices Sunnyvale California USA
TM
is a trademark of National Semiconductor Corporation
The NSBMC290 Burst Mode Memory Control-
is
TM
Typical System Configuration
functionally
TM
-16 -20 -25 -33
Streamlined Instruction Proces-
TL V 11803
equivalent
to
the
The function of NSBMC290 is to interface the page mode
access protocol of dynamic RAMs with the more general
burst mode access protocol supported by the Am29000 lo-
cal channel The device manages a double banked arrang-
ment of dynamic RAMs such that when burst accesses are
permitted data can be read or written at the rate of one
word per system clock cycle
Packaged as a 124 pin PGA or 132 pin PQFP the
NSBMC290 drives memory arrays directly thus minimizing
design complexity and package count
Features
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Interfaces directly to Am29000 Local Channel
Manages Page Mode Dynamic Memory devices
Supports DRAMs from 64 KB to 16 MB
Manages Instruction and or Data Memory
Very Low Power Consumption
On-Chip Memory Address Multiplexer Drivers
Flexible Instruction Data Bus Buffer Management
Software-Configured operational parameters
Auto-Configured Bank Size and Location
High-Speed CMOS Technology
TL V 11803 – 1
Logic Symbol
RRD-B30M115 Printed in U S A
TL V 11803 – 2
July 1993

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NSBMC290VF Summary of contents

Page 1

TM NSBMC290 -16 -20 -25 -33 Burst Mode Memory Controller General Description The NSBMC290 is functionally equivalent V29BMC The NSBMC290 Burst Mode Memory Control- TM ler is a single chip device designed to simplify the imple- mentation of burst mode ...

Page 2

... Connection Diagrams PQFP Order Number NSBMC290VF NS Package Number VF132A PGA Bottom View Order Number NSBMC290UP See NS Package Number UP124A 11803 – 11803– 9 ...

Page 3

Pin Descriptions PGA Pin QFP Pin Signal A10 ...

Page 4

Pin Descriptions Am29000 INTERFACE The following pins have the same function as their counterparts on the Am29000 and are designed to be connected directly to the Am29000 Synchronous Channel Interface Pin A0-31 Address Bus (Input) The address bus transfers byte ...

Page 5

Pin Descriptions (Continued) MEMORY INTERFACE The NSBMC290 is designed to drive a memory array orga- nized as 2 banks each of 32 bits The address and control signals for the memory array are output through high current Pin A(A B)0–10 ...

Page 6

Functional Description PRODUCT OVERVIEW The NSBMC290 is designed to simplify the interface be- tween the Am29000 high-speed synchronous channel and dynamic memories This integrated circuit responds to all defined instruction and data access modes of the Am29000 and handles all ...

Page 7

Functional Description (Continued) BLOCK ADDRESS Once configured a NSBMC290 only responds to addresses within the block address range configured grammed value corresponds to the starting address of the block while the size of the block is determined by the size ...

Page 8

Functional Description (Continued) TABLE II Buffer Control Signals and the Memory Bank for Which they are active Simple Pipeline Cycle Signal Name Read DBTX A B DBTXa A DBTXb B DBCE A B DBCEa A DBCEb B IBTX A B ...

Page 9

Functional Description (Continued) INTERCONNECT DETAILS The NSBMC290 may be applied in designs where instruc- tion and data memories are separated or in designs where a single memory space is used for both instruction and data In split instruction data designs ...

Page 10

Typical Application (Continued) 10 ...

Page 11

CPU INTERFACE The NSBMC290 interface to the Am29000 has been de- signed for direct interconnect Normally it is not necessary to place other logic devices between the processor NSBMC290 and memory with the exception of Instruction Data bus buffers The ...

Page 12

Typical Application (Continued) FIGURE 4 Burst Read Sequence (Illustrating Burst Suspension) BURST ACCESS SEQUENCE When Burst access has been established the NSBMC290 generates the signal sequence of Figure 5 This access se- quence will continue until either canceled or suspended ...

Page 13

Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage ( Input Voltage ( Input Current ...

Page 14

Timing Parameters DBTX DBTXa DBTXb DBCE DBCEa DBCEb IBTX IBTXa IBTXb FIGURE 5 Simple Access Timing 11803 – 10 ...

Page 15

AC Timing Parameters (Unless otherwise stated V Symbol Description 1 t BlNV Setup BSU 2 t BINV Hold Request Sync Setup Time RQSU 4 t Request Sync Hold Time RQH 5 t Synchronous Input Setup SU 5A ...

Page 16

AC Timing Parameters (Continued) TXa IBTXa DBTXa CEa IBCEa DBCE TXb Note Buffer control signal timing is illustrated using the mode dependent signal naming convention (See page shown the switching behavior is typical of ...

Page 17

Release Notes for NSBMC290 Revision ‘‘A’’ A NOTE ON THE OPERATION OF THE Am29000 characteristic of the Am29000 (Rev D) that it can de- assert the IBREQ signal independently of the current state of IRDY and IBACK ...

Page 18

Ordering Code Information National Semiconductor Mode Burst Mode Controller Processor 290 AMD 29000 Family e NS BMC 290 Frequency 16 MHz 20 MHz 25 MHz 33 MHz Packaging 124-Lead PPGA 132-Lead PQFP ...

Page 19

Physical Dimensions inches (millimeters) Pin Grid Array (PGA) Order Number NSBMC290UP NS Package Number UP124A 19 ...

Page 20

... National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications Plastic Quad Flatpak (PQFP) Order Number NSBMC290VF NS Package Number VF132A 2 A critical component is any component of a life ...

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