PSD4235G2V-10U STMICROELECTRONICS [STMicroelectronics], PSD4235G2V-10U Datasheet - Page 13

• Manufacturer Part Number: PSD4235G2V-10U
• Description: Flash In-System Programmable (ISP) Peripherals for 16-bit MCUs
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PB0-PB7
PC0-PC7
PD0
PD1
PD2
PD3
PE0
PE1
PE2
PE3
Pin Name
61-68
41-48
79
80
1
2
71
72
73
74
Pin
I/O
CMOS
or
Open
Drain
I/O
CMOS
I/O
CMOS
or
Open
Drain
I/O
CMOS
or
Open
Drain
I/O
CMOS
or
Open
Drain
I/O
CMOS
or
Open
Drain
I/O
CMOS
or
Open
Drain
I/O
CMOS
or
Open
Drain
I/O
CMOS
or
Open
Drain
I/O
CMOS
or
Open
Drain
Type
These pins make up Port B. These port pins are configurable and can have the
following functions:
1. MCU I/O – standard output or input port.
2. CPLD Macrocell (McellB0-McellB7) outputs.
3. Latched, transparent or registered PLD inputs (can also be PLD input for address A16
These pins make up Port C. These port pins are configurable and can have the
following functions:
1. MCU I/O – standard output or input port.
2. External Chip Select (ECS0-ECS7) outputs.
3. Latched, transparent or registered PLD inputs (can also be PLD input for address A16
PD0 pin of Port D. This port pin can be configured to have the following functions:
1. ALE/AS input – latches address on ADIO0-ADIO15.
2. AS input – latches address on ADIO0-ADIO15 on the rising edge.
3. MCU I/O – standard output or input port.
4. Transparent PLD input (can also be PLD input for address A16 and above).
PD1 pin of Port D. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Transparent PLD input (can also be PLD input for address A16 and above).
3. CLKIN – clock input to the CPLD Macrocells, the APD Unit’s Power-down counter,
PD2 pin of Port D. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Transparent PLD input (can also be PLD input for address A16 and above).
3. PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory and
PD3 pin of Port D. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Transparent PLD input (can also be PLD input for address A16 and above).
3. WRH – for 16-bit data bus, WRITE to high byte, active low.
PE0 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. TMS Input for the JTAG Serial Interface.
PE1 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. TCK Input for the JTAG Serial Interface.
PE2 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. TDI input for the JTAG Serial Interface.
PE3 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. TDO output for the JTAG Serial Interface.
and above).
and above).
and the CPLD AND Array.
I/O. When High, the PSD memory blocks are disabled to conserve power. The falling
edge of this signal can be used to get the device out of Power-down mode.
Description
PSD4256G6V
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