UC384XBD MOTOROLA [Motorola, Inc], UC384XBD Datasheet - Page 7

• Manufacturer Part Number: UC384XBD
• Description: HIGH PERFORMANCE CURRENT MODE CONTROLLERS
• Manufacturer: MOTOROLA [Motorola, Inc]

fixed frequency, current mode controllers. They are
specifically designed for Off–Line and dc–to–dc converter
applications offering the designer a cost–effective solution
with minimal external components. A representative block
diagram is shown in Figure 15.
Oscillator
selected for the timing components R T and C T . Capacitor C T
is charged from the 5.0 V reference through resistor R T to
approximately 2.8 V and discharged to 1.2 V by an internal
current sink. During the discharge of C T , the oscillator
generates an internal blanking pulse that holds the center
input of the NOR gate high. This causes the Output to be in a
low state, thus producing a controlled amount of output
deadtime. An internal flip–flop has been incorporated in the
UCX844/5B which blanks the output off every other clock
cycle by holding one of the inputs of the NOR gate high. This
in combination with the C T discharge period yields output
deadtimes programmable from 50% to 70%. Figure 1 shows
R T versus Oscillator Frequency and Figure 2, Output
Deadtime versus Frequency, both for given values of C T .
Note that many values of R T and C T will give the same
oscillator frequency but only one combination will yield a
specific output deadtime at a given frequency. The oscillator
thresholds are temperature compensated to within 6% at 50
kHz. Also, because of industry trends moving the UC384X
into higher and higher frequency applications, the UC384XB
is guaranteed to within 10% at 250 kHz.
to frequency–lock the converter to an external system clock.
This can be accomplished by applying a clock signal to the
circuit shown in Figure 17. For reliable locking, the
free–running oscillator frequency should be set about 10%
less than the clock frequency. A method for multi–unit
synchronization is shown in Figure 18. By tailoring the clock
waveform, accurate Output duty cycle clamping can be
achieved to realize output deadtimes of greater than 70%.
Error Amplifier
inverting input and output is provided. It features a typical dc
voltage gain of 90 dB, and a unity gain bandwidth of 1.0 MHz
with 57 degrees of phase margin (Figure 5). The
non–inverting input is internally biased at 2.5 V and is not
pinned out. The converter output voltage is typically divided
down and monitored by the inverting input. The maximum
input bias current is –2.0
voltage error that is equal to the product of the input bias
current and the equivalent input divider source resistance.
compensation (Figure 28). The output voltage is offset by two
diode drops ( 1.4 V) and divided by three before it connects
to the inverting input of the Current Sense Comparator. This
guarantees that no drive pulses appear at the Output (Pin 6)
when Pin 1 is at its lowest state (V OL ). This occurs when the
MOTOROLA ANALOG IC DEVICE DATA
The UC3844B, UC3845B series are high performance,
The oscillator frequency is programmed by the values
In many noise–sensitive applications it may be desirable
A fully compensated Error Amplifier with access to the
The Error Amp Output (Pin 1) is provided for external loop
A which can cause an output
UC3844B, 45B UC2844B, 45B
OPERATING DESCRIPTION
power supply is operating and the load is removed, or at the
beginning of a soft–start interval (Figures 20, 21). The Error
Amp minimum feedback resistance is limited by the
amplifier’s source current (0.5 mA) and the required output
voltage (V OH ) to reach the comparator’s 1.0 V clamp level:
Current Sense Comparator and PWM Latch
controller, whereby output switch conduction is initiated by
the oscillator and terminated when the peak inductor current
reaches the threshold level established by the Error Amplifier
Output/Compensation (Pin 1). Thus the error signal controls
the peak inductor current on a cycle–by–cycle basis. The
Current Sense Comparator PWM Latch configuration used
ensures that only a single pulse appears at the Output during
any given oscillator cycle. The inductor current is converted
to a voltage by inserting the ground–referenced sense
resistor R S in series with the source of output switch Q1. This
voltage is monitored by the Current Sense Input (Pin 3) and
compared to a level derived from the Error Amp Output. The
peak inductor current under normal operating conditions is
controlled by the voltage at Pin 1 where:
supply output is overloaded or if output voltage sensing is
lost. Under these conditions, the Current Sense Comparator
threshold will be internally clamped to 1.0 V. Therefore the
maximum peak switch current is:
becomes desirable to reduce the internal clamp voltage in
order to keep the power dissipation of R S to a reasonable
level. A simple method to adjust this voltage is shown in
Figure 19. The two external diodes are used to compensate
the internal diodes, yielding a constant clamp voltage over
temperature. Erratic operation due to noise pickup can result
if there is an excessive reduction of the I pk(max) clamp
voltage.
waveform can usually be observed and may cause the power
supply to exhibit an instability when the output is lightly
loaded. This spike is due to the power transformer
interwinding capacitance and output rectifier recovery time.
The addition of an RC filter on the Current Sense Input with a
time constant that approximates the spike duration will
usually eliminate the instability (refer to Figure 23).
The UC3844B, UC3845B operate as a current mode
Abnormal operating conditions occur when the power
When designing a high power switching regulator it
A narrow spike on the leading edge of the current
R f(min)
I pk =
3.0 (1.0 V) + 1.4 V
I pk(max) =
0.5 mA
V (Pin 1) – 1.4 V
3 R S
1.0 V
R S
= 8800
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