LM26003MH NSC [National Semiconductor], LM26003MH Datasheet - Page 14

• Manufacturer Part Number: LM26003MH
• Description: 3A Switching Regulator with High Efficiency Sleep Mode
• Manufacturer: NSC [National Semiconductor]

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Where Co is the output capacitance, Ro is the load resistance,
Re is the output capacitor ESR, and fsw is the switching fre-
quency.
The effects of slope compensation and current sense gain are
included in this equation. However, the equation is an ap-
proximation intended to simplify loop compensation calcula-
tions.
Since fp is determined by the output network, it shifts with
loading. Determine the range of frequencies (fpmin/max)
across the expected load range. Then determine the com-
pensation values as described below and shown in Figure
10.
1. The compensation network automatically introduces a low
frequency pole (fpc), which is close to 0 Hz.
2. Once the fp range is determined, R5 should be calculated
using:
Where B is the desired feedback gain in v/v between fp and
fz, and gm is the transconductance of the error amplifier. A
gain value around 10 dB (3.3v/v) is generally a good starting
point. Bandwidth increases with increasing values of R3.
3. Next, place a zero (fzc) near fp using C5. C5 can be de-
termined with the following equation:
The selected value of C5 should place fzc within a decade
above or below fpmax and not less than fpmin. A higher C5
value (closer to fpmin) generally provides a more stable loop,
but too high a value will slow the transient response time.
Conversely, a smaller C5 value will result in a faster transient
response, but lower phase margin.
FIGURE 10. Compensation Network
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4. A second pole (fpc1) can also be placed at fz. This pole can
be created with a single capacitor, C4. The minimum value
for this capacitor can be calculated by:
C4 may not be necessary in all applications. However if the
operating frequency is being synchronized below the nominal
frequency, C4 is recommended. Although it is not required for
stability, C4 is very helpful in suppressing noise.
A phase lead capacitor can also be added to increase the
phase and gain margins. The phase lead capacitor is most
helpful for high input voltage applications or when synchro-
nizing to a frequency greater than nominal. This capacitor,
shown as C11 in Figure 10, should be placed in parallel with
the top feedback resistor, R1.
C11 introduces an additional zero and pole to the compen-
sation network. These frequencies can be calculated as
shown below:
A phase lead capacitor will boost loop phase around the re-
gion of the zero frequency, fzff. fzff should be placed some-
what below the fpz1 frequency set by C4. However, if C11 is
too large, it will have no effect.
PCB Layout
Good board layout is critical for switching regulators such as
the LM26003. First, the ground plane area must be sufficient
for thermal dissipation purposes, and second, appropriate
guidelines must be followed to reduce the effects of switching
noise.
Switch mode converters are very fast switching devices. In
such devices, the rapid increase of input current combined
with parasitic trace inductance generates unwanted Ldi/dt
noise spikes at the SW node and also at the VIN node. The
magnitude of this noise tends to increase as the output current
increases. This parasitic spike noise may turn into electro-
magnetic interference (EMI) and can also cause problems in
device performance. Therefore, care must be taken in layout
to minimize the effect of this switching noise.
The current sensing circuit in current mode devices can be
easily affected by switching noise. This noise can cause duty-
cycle jitter which leads to increased spectrum noise. Although
the LM26003 has 150 ns blanking time at the beginning of
every cycle to ignore this noise, some noise may remain after
the blanking time. Following the important guidelines below
will help minimize switching noise and its effect on current
sensing.
The switch node area should be as small as possible. The
catch diode, input capacitors, and output capacitors should
be grounded to the same local ground, with the bulk input
capacitor grounded as close as possible to the catch diode
anode. Additionally, the ground area between the catch diode
and bulk input capacitor is very noisy and should be some-
what isolated from the rest of the ground plane.