ADP1046-100-EVALZ AD [Analog Devices], ADP1046-100-EVALZ Datasheet - Page 82

• Manufacturer Part Number: ADP1046-100-EVALZ
• Description: Digital Controller for Isolated
• Manufacturer: AD [Analog Devices]

ADP1046
Table 120. Register 0x78—Volt-Second Balance Settings (SR1 and SR2 Pins)
Bits
7
6
5
4
3
2
1
0
Table 121. Register 0x79—SR Delay Compensation
Bits
[7:6]
[5:0]
Table 122. Register 0x7A—Filter Transitions
Bits
[7:6]
[5:3]
2
[1:0]
Table 123. Register 0x7B—PGOOD1 Flag Masking
Bits
7
6
5
4
3
2
1
0
Bit Name
Modulate enable, t
t
Modulate enable, t
t
Modulate enable, t
t
Modulate enable, t
t
Bit Name
Reserved
SR driver delay
Bit Name
Reserved
HF ADC configuration
Enable soft transition
Transition speed
Bit Name
Soft start flag
CS1 fast OCP
CS1 accurate OCP
CS2 accurate OCP
UVP
Local OVP (fast and
accurate)
Load OVP
OrFET
9
10
11
12
sign
sign
sign
sign
9
10
11
12
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Setting this bit enables modulation from balance control on the SR1 rising edge, t
0 = positive sign. Increase of balance control modulation moves t
1 = negative sign. Increase of balance control modulation moves t
Setting this bit enables modulation from balance control on the SR1 falling edge, t
0 = positive sign. Increase of balance control modulation moves t
1 = negative sign. Increase of balance control modulation moves t
Setting this bit enables modulation from balance control on the SR2 rising edge, t
0 = positive sign. Increase of balance control modulation moves t
1 = negative sign. Increase of balance control modulation moves t
Setting this bit enables modulation from balance control on the SR2 falling edge, t
0 = positive sign. Increase of balance control modulation moves t
1 = negative sign. Increase of balance control modulation moves t
Description
Reserved.
These bits specify the 6-bit representation of the SR delay in steps of 5 ns.
000000 = 0 ns.
111111 = 63 ns × 5 ns = 315 ns.
Description
Reserved.
Set these bits to 001 at all times for proper operation.
Setting this bit enables a soft transition between filter settings to minimize output transients.
All four parameters of each filter are linearly transitioned to the new value.
These bits set the transition speed from one filter to another. The filter changes in 32 steps;
each step is applied at the multiple of switching cycles (t
Bit 1
0
0
1
1
Description
If set to 1, this flag is ignored by PGOOD1. This bit must be set to 0 to enable proper PGOOD1
debounce timing after the end of the soft start ramp.
If set to 1, this flag is ignored by PGOOD1.
If set to 1, this flag is ignored by PGOOD1.
If set to 1, this flag is ignored by PGOOD1.
If set to 1, this flag is ignored by PGOOD1.
If set to 1, this flag is ignored by PGOOD1.
If set to 1, this flag is ignored by PGOOD1.
If set to 1, this flag is ignored by PGOOD1.
Bit 0
0
1
0
1
Rev. 0 | Page 82 of 96
Speed (t
32 t
8 t
2 t
1 t
SW
SW
SW
SW
(total transition time = 8 × 32 t
(total transition time = 64 × t
(total transition time = 32 × t
(total transition time = 32 × 32 t
SW
= One Switching Cycle)
SW
) specified by these bits.
SW
SW
SW
)
)
SW
= 256 × t
9
10
11
12
= 1024 × t
9
10
11
12
right.
right.
right.
right.
left.
left.
left.
left.
SW
)
SW
)
Data Sheet
9
11
.
10
12
.
.
.