A3949_04 ALLEGRO [Allegro MicroSystems], A3949_04 Datasheet - Page 2

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A3949_04

Manufacturer Part Number
A3949_04
Description
DMOS Full-Bridge Motor Driver
Manufacturer
ALLEGRO [Allegro MicroSystems]
Datasheet
Control Logic Table
* To prevent reversal of current during fast decay SR (synchronous rectifi cation), the outputs
go to the high impedance state as the current approaches zero.
PHASE ENABLE MODE
ENABLE
PHASE
SLEEP
MODE
X
X
1
0
1
0
1
1
0
0
0
X
.22 μF
25 V
Gate Supply
Low Side
X
X
X
1
0
0
Functional Block Diagram
VREG
Control
Logic
SLEEP
1
1
1
1
1
0
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
OSC
OUTA
Hi-Z
DMOS Full Bridge
H
H
L
L
L
CP1
Charge
0.1 μF
Pump
DMOS Full-Bridge Motor Driver
OUTB
Hi-Z
H
H
L
L
L
CP2
Brake (slow decay)
VCP
VBB
OUTA
OUTB
SENSE
GND
GND
Fast decay SR*
Fast decay SR*
0.1 μF
Sleep mode
Function
Forward
Reverse
0.1 μF
100 μF
Supply
Load
A3949
2

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