R2J20701NP_08 RENESAS [Renesas Technology Corp], R2J20701NP_08 Datasheet
R2J20701NP_08
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R2J20701NP_08 Summary of contents
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R2J20701NP Peak Current Mode Synchronous Buck Controller with Power MOS FETs Description This all-in-one SiP for POL (point-of-load) applications is a multi-chip module incorporating a high-side MOS FET, low-side MOS FET, and PWM controller in a single QFN package. The ...
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R2J20701NP Application Circuit Example SYNC REG5 TRK- SGND REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Page Controller Chip VIN ( VOUT (1.8 V) ...
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R2J20701NP Block Diagram REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Page ...
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R2J20701NP Pin Arrangement 14 13 VIN 15 VIN 16 VIN 17 VIN 18 VIN 19 VIN PGND 22 PGND 23 PGND 24 PGND 25 PGND 26 PGND 27 PGND Package: 56-pin QFN (8 mm ...
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R2J20701NP Pin Description Pin Name Pin No. VIN Input voltage for the buck converter 21 Switching node. Connect a choke coil between the SW pin and dc output node of the converter. ...
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R2J20701NP Absolute Maximum Ratings Item Power dissipation Average output current Input voltage Switch node voltage BOOT pin voltage ON/OFF pin voltage SYNC pin voltage Voltage on other pins REG5 current Ishare current TRK-SS dc current IREF current EO sink current ...
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R2J20701NP Electrical Characteristics Item Supply VIN start threshold VIN shutdown threshold UVLO hysteresis Input bias current Input shutdown current 5-V Output voltage regulator Line regulation Load regulation 5.25-V Output voltage regulator Remote Disable threshold On/off Enable threshold Input current Reference ...
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R2J20701NP Item Current CS current ratio sense Leading edge blanking time CS comparator delay to output OCP comparator threshold on CS pin Hiccup interval RAMP offset voltage CS offset current Note: 1. These are reference values for design and have ...
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R2J20701NP Description of Operation Peak Current Control The control IC operates in a current-programmed control mode, in which the output of the converter is controlled by the choice of the peak current from the high-side MOS FET. The current from ...
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R2J20701NP Oscillator and Pulse Generator The frequency of oscillation is set by the value of the external capacitor connected to the CT pin. This frequency is twice as high as the actual switching frequency. The frequencies are determined by the ...
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R2J20701NP Application Example Start-up Settings Case 1) Standalone or master chip in parallel operation With the RC network on the TRK-SS pin, the voltage on the pin should ramp up slowly. REG5 R TRK-SS C Case 2) Coincident tracking The ...
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R2J20701NP Case 3) Retiometric tracking The TRS-SS of channel two is tied to TRK-SS of channel 1. No cross talk is observed between the channels. REG5 R Channel 1 TRK-SS C REG5 R Channel 1 TRK-SS C Output voltage REJ03G1459-0400 ...
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R2J20701NP Case 4) Current sharing or two-phase operation In the case of master–slave operation, the TRK-SS pin on the master device should be attached network for soft starts. TRK-SS pins of slave devices should be tied to ...
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R2J20701NP Output Voltage Setting The error amplifier of the device has an accurate 0.6 V reference voltage. Feedback thus leads to a voltage of about 0 the FB pin once the converter system has stabilized, so the output ...
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R2J20701NP Rf Vout Design example Specification 360 nH 600 µF, Fsw = 500 kHz, Vin = 12 V, Vout = 1 kΩ kΩ, RCS = 750 ...
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R2J20701NP Equation ( RCS SQRT {Vin 18500 / 750 = 2 SQRT { 360 nH 106.56 = SQRT {70.687} = 12.674 The frequency of the pole established by the ...
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R2J20701NP Study of Vout Accuracy The nominal output voltage is calculated as Vout = VFB × ( ……(6) Here, the typical feedback voltage is 0 The accuracy of Vout is strongly dependent on ...
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R2J20701NP The accuracy of Vout can be estimated by using equation (10). For example, if Vout (typical) = 1.8 V, resistance variation is 1% (i.e. K1 1.01 and 0.99), and VFB = 594 mV to 606 mV: Vout ...
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R2J20701NP Current Sharing Simply tie the Ishare pins together SYNC Device 1 Ishare SYNC Device 2 Ishare SYNC Device N ( Ishare External Synchronization External clock External clock; Frequency range: 200 kHz to 1 ...
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R2J20701NP Current Sharing and Synchronization Tie the Ishare and SYNC pins together SYNC Device 1 (Master) Ishare SYNC Device 2 Ishare SYNC Device N ( Ishare Two-Phase Operation Tie the Ishare and SYNC pins together. SYNC Device 1 ...
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R2J20701NP Timing Chart Peak Current Control Max. Duty (Internal signal) RES (Internal signal) TLD 50 ns (typ.) RAMP 0 V VIN obtain stable operation, settings should be such that the level on the switching node is ...
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R2J20701NP Oscillator and Pulse Generator 1. Standalone operation or operation as the master chip in a parallel configuration with other chips SYNC 0 V Max. Duty (Internal signal (typ.) RES (Internal ...
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R2J20701NP 2. Operation as a slave chip (simple synchronous operation) 0 SYNC (Input Max. Duty (Internal signal (typ.) RES (Internal signal) SYNC frequency range: 200 kHz to 1 MHz Note: ...
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R2J20701NP Hiccup Operation when the Over-Current Limit (OCL) is Reached TRK-SS 1 1024 pulses skipped 0 V Note: Propagation delay is ignored. REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Page Detected OCL 1024 pulses skipped Normal operation ...
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R2J20701NP Main Characteristics VH vs. Temperature 7.7 7.6 7.5 7.4 7.3 7.2 7.1 7.0 6.9 6.8 6.7 –50 – Temperature (°C) Vreg vs. Temperature 5.10 5.05 5.00 4.95 4.90 –50 – Temperature (°C) REJ03G1459-0400 ...
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R2J20701NP Fsync vs. Temperature 500 490 480 470 460 450 440 430 –50 – Temperature (°C) Voff vs. Temperature 1.45 1.40 1.35 1.30 1.25 1.20 1.15 1.10 1.05 –50 – ...
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R2J20701NP Package Dimensions JEITA Package Code RENESAS Code — PWQN0056KB REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Page Previous Code MASS[Typ.] — 0.17g A B 1.00 ...
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Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained ...