A6841 ALLEGRO [Allegro MicroSystems], A6841 Datasheet - Page 4

• Manufacturer Part Number: A6841
• Description: DABiC-5 8-Bit Serial Input Latched Sink Drivers
• Manufacturer: ALLEGRO [Allegro MicroSystems]

NOTE: Timing is representative of a 10 MHz clock. Higher speeds may be
attainable; operation at high temperatures will reduce the specifi ed maxi-
mum clock frequency.
Powering-on with the inputs in the low state ensures that the registers and
latches power-on in the low state (POR).
S
0 to logical 1 transition of the CLOCK input pulse. On succeeding CLOCK
pulses, the registers shift data information towards the SERIAL DATA OUT-
PUT. The SERIAL DATA must appear at the input prior to the rising edge of the
CLOCK input waveform.
erial Data present at the input is transferred to the shift register on the logical
OUTPUT ENABLE
DABiC-5 8-Bit Serial Input Latched Sink Drivers
OUTPUT ENABLE
Key
B
C
D
E
A
DATA OUT
STROBE
DATA IN
CLOCK
SERIAL
SERIAL
OUT
Data Active Time Before Clock Pulse (Data Set-Up Time)
Data Active Time After Clock Pulse (Data Hold Time)
Clock Pulse Width
Time Between Clock Activation and Strobe
Strobe Pulse Width
Timing Requirements and Specifi cations
OUT
N
N
A
(Logic Levels are V
DATA
50%
B
Description
C
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Worcester, Massachusetts 01615-0036 [phone]
50%
LOW = ALL OUTP UTS E NABLE D
D
50%
50%
t
p(CH-SQX)
t
dis(BQ)
Information present at any register is transferred to the respective latch
when the STROBE is high (serial-to-parallel conversion). The latches will
continue to accept new data as long as the STROBE is held high. Applica-
tions where the latches are bypassed (STROBE tied high) will require that
the OUTPUT ENABLE input be high during serial data entry.
When the OUTPUT ENABLE input is high, all of the output buffers are
disabled (OFF). The information stored in the latches or shift register is not
affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE
input low, the outputs are controlled by the state of their respective latches.
DD
50%
HIGH = ALL OUTP UTS BLANKE D (DIS ABLE D)
and Ground)
E
t
p(STH-QL)
t
10%
p(STH-QH)
t
en(BQ)
DATA
90%
t
Symbol
DATA
t
r
t
w(STH)
t
t
w(CH)
t
su(D)
su(C)
h(D)
10%
90%
Time (ns)
50%
100
25
25
50
50
t
DATA
f
A6841
4