FAN8460MPX FAIRCHILD [Fairchild Semiconductor], FAN8460MPX Datasheet - Page 12

• Manufacturer Part Number: FAN8460MPX
• Description: Single Phase Full Wave BLDC Motor Driver with Variable Speed Control
• Manufacturer: FAIRCHILD [Fairchild Semiconductor]

FAN8460MTC/FAN8460MP
output PWM duty is proportional to input PWM duty with some dead band. The output PWM frequency is defined by external
capacitor, C
the motor speed according to digital VPWM input and V
Table 1.
4.3 PWM Speed Control using External PWM Input(Scheme 3)
This scheme indicates that digital PWM input signal becomes directly output PWM signal. In other word, frequency and duty
of output PWM driving signal is the same as this digital PWM input. In case input PWM frequency is very low, active filter
needs large value of capacitor to make speed control voltage in scheme 2. This scheme dosen’t need filter capacitor and has
good input/output characteristics. This means that there is no deadband and output signals are synchronized with input VPWM
signal as shown in figure6.
4.4 Offset comparator(Thermistor open protection)
If under 100mV difference between VREF and VCON, fan motor runs at full speed.
5 Locked Rotor Protection with Open Collector Output and Automatic Restart
When the rotor is locked, there is no change in input signal of hall amplifier and thus a internal T
A capacitor (C
(V
turned-off to protect motor during T
threshold, V
V
discharging repeat until locked condition is removed, or FAN8460MTC/FAN8460MP is powered down. The overall time chart
is shown in figure.6. The auto- retry time (T
(T
12
Thermistor Input
CLD
LOCK
LDCL
180K
PWM Input
ramps up again and one of two outputs is turned on depending on locked rotor position during T
Mode
) are proportional to external capacitor, C
) resulting from no Tzero pulse. When the voltage, V
.
Operation Tables
T.
12
LDCL
So there is no relationship between VPWM input frequency and output PWM frequency. Table 1 summarizes
LD
CT
VPWM
) connected LD pin is continually charged by internal current source (i
, V
Decoder
PWM
CLD
VPWM
5
GND
H/L
starts to decrease with internal current sink (i
H
L
20K
Figure 6. Interface and it’s Related Waveforms Scheme3
11
Depend on mother board PWM signal
OFF
VCON
Depend on thermistor resistance
6.2K
R
Reference
and the alarm output (AL) becomes floating high. When the V
PWM
ON
VCC
2V
4
), the motor protection time (T
VREF
LD.
VCON
Each value can be calculated as follows;
H
L
VCON
CLD on
VPWM
OUTA
OUTB
LD pin, reaches V
H -
H+
LDD
) to the low threshold, V
OFF
The higher TEMP, the faster fan speed
) and the locked rotor detection time
proportional to PWM input duty
LDCL
LDC
Speed Condition
) to the internal threshold
, high side output power TR is
Full Speed
ZERO
LDCP
Stop
ON
CLD
pulse is not observed.
. At that time, the
. The charging and
reaches upper