LP8720TLE NSC [National Semiconductor], LP8720TLE Datasheet - Page 10

• Manufacturer Part Number: LP8720TLE
• Description: One Step-Down DC/DC and Five Linear Regulators with I2C Compatible Interface
• Manufacturer: NSC [National Semiconductor]

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LDO1_EN LDO2_EN
LDO3_EN LDO4_EN
LDO5_EN BUCK_EN
SLEEP_MODE
DVS_V2/V1
LDO1_PULLDOWN
LDO2_PULLDOWN
LDO3_PULLDOWN
LDO4_PULLDOWN
LDO5_PULLDOWN
BUCK_PULLDOWN
APU_TSD
TSD
TSD_EW
TSD_INT
TSD_EW
TSD_MASK
TSD_EW_MASK
Register 0x08
Register 0x09
Register 0x0A (Read Only)
Register 0x0B (Read Only)
Note 1: all reads from this register are destructive (all bits are reset to 0 after reading).
Note 2: read form this register releases IRQ_N-pin (if was pushed down).
Register 0x0C
In STANDBY mode
1 – During next START UP sequence will be enabled.
0 – During next START UP sequence will be NOT enabled.
For proper operation output having “111 NO start up” should
have corresponding enable bit 0 (disable).
1 – SLEEP
0 – normal
This bit has effect only if EXT_SLEEP_CONTROL=0 (register 0x00)
1 – buck voltage is BUCK_V1[4:0]
0 – buck voltage is BUCK_V2[4:0]
This bit has effect only if EXT_DVS_CONTROL=0 (register 0x00)
1 – Pull down enabled
0 – Pull down disabled
This bit defines either to reset registers or not before LP8720 automatically starts START UP sequence
form Thermal Shutdown after cooling down if EN-pin is High.
1 – No change to registers – registers content stays the same as before Thermal Shutdown.
0 – Reset registers to default values before START UP from Thermal Shutdown.
1 – device is in Thermal Shutdown.
0 – device is NOT in Thermal Shutdown .
1 – device temperature is higher than Thermal Shutdown Early Warning threshold.
0 – device temperature is lower than Thermal Shutdown Early Warning threshold.
1 – Interrupt that was caused by Thermal Shutdown
0 – No Interrupt that was caused by Thermal Shutdown
1 – Interrupt that was caused by Thermal Shutdown Early Warning
0 – No Interrupt that was caused by Thermal Shutdown Early Warning
1 – TSD interrupt is masked
0 – TSD interrupt is NOT masked
1 – TSD_EW interrupt is masked
0 – TSD_EW interrupt is NOT masked
10
In IDLE mode the bit has immediate
effect.
1 – Enable
0 – Disable