TCN75-3.3MPA TELCOM [TelCom Semiconductor, Inc], TCN75-3.3MPA Datasheet - Page 4

• Manufacturer Part Number: TCN75-3.3MPA
• Description: 2-WIRE SERIAL TEMPERATURE SENSOR AND THERMAL MONITOR
• Manufacturer: TELCOM [TelCom Semiconductor, Inc]

PRELIMINARY INFORMATION
A0 in the serial bit stream must match the states of the A2,
A1 and A0 address inputs for the TCN75 to respond with an
Acknowledge (indicating the TCN75 is on the bus and ready
to accept data). The Slave Address is represented by:
TCN75 Slave Address
Comparator/Interrupt Modes
the TCN75 is in Comparator Mode or Interrupt Mode.
Comparator Mode is designed for simple thermostatic op-
eration. INT/CMPTR will go active anytime TEMP exceeds
T
active until TEMP falls below T
to its inactive state. The state of INT/CMPTR is maintained
in shutdown mode when the TCN75 is in comparator mode.
In Interrupt Mode, INT/CMPTR will remain active indefi-
nitely, even if TEMP falls below T
read via the 2-wire bus. Interrupt Mode is better suited to
interrupt driven microprocessor-based systems. The INT/
CMPTR output may be wire-OR'ed with other interrupt
sources in such systems. Note that a pull-up resistor is
necessary on this pin since it is an open-drain output.
Entering Shutdown Mode will unconditionally reset INT/
CMPTR when in Interrupt Mode.
SHUTDOWN MODE
register (CONFIG) the TCN75 enters its low-power shut-
down mode (I
digital conversion process is halted. The TCN75's bus
interface remains active and TEMP, T
read from and written to. Transitions on SDA or SCL due to
external bus activity may increase the standby power con-
sumption. If the TCN75 is in Interrupt Mode, the state of INT/
CMPTR will be RESET upon entering shutdown mode.
Fault Queue
CMPTR the TCN75 may be programmed to filter out tran-
sient events. This is done by programming the desired value
into the Fault Queue. Logic inside the TCN75 will prevent the
device from triggering INT/CMPTR unless the programmed
number of sequential temperature-to-digital conversions
yield the same qualitative result. In other words, the value
reported in TEMP must remain above T
for the consecutive number of cycles programmed in the
Fault Queue. Up to a six-cycle "filter" may be selected. See
Register Set and Programmer's Model .
TCN75-04 6/16/97
TCN75
SET
MSB
1
INT/CMPTR behaves differently depending on whether
When the appropriate bit is set in the configuration
To lessen the probability of spurious activation of INT/
. When in Comparator Mode, INT/CMPTR will remain
0
DD
= 1 A, typical) and the temperature-to-
0
1
HYST
HYST
, whereupon it will reset
A2
SET
, until any register is
SET
, and T
or below T
A1
HYST
may be
LSB
A0
HYST
4
Serial Port Operation
(SDA) form a 2-wire bidirectional serial port for programming
and interrogating the TCN75. The following conventions are
used in this bus scheme:
TCN75 Serial Bus Conventions
Term
Transmitter
Receiver
Master
Slave
Start
Stop
ACK
NOT Busy
Data Valid
a CPU or microcontroller, acting as the Master, which
provides the clock signal for all transfers. The TCN75 always
operates as a Slave. This serial protocol is illustrated in
Figure 2. All data transfers have two phases; and all bytes
are transferred MSB first. Accesses are initiated by a start
condition (START), followed by a device address byte and
one or more data bytes. The device address byte includes
a Read/Write selection bit. Each access must be terminated
by a Stop Condition (STOP). A convention called Acknowl-
edge (ACK) confirms receipt of each byte. Note that SDA
can change only during periods when SCL is LOW (SDA
changes while SCL is HIGH are reserved for Start and Stop
Conditions).
Start Condition (START)
lines for a start condition (a HIGH to LOW transition of SDA
while SCL is HIGH), and will not respond until this condition
is met.
The Serial Clock input (SCL) and bidirectional data port
All transfers take place under control of a host, usually
The TCN75 continuously monitors the SDA and SCL
SENSOR AND THERMAL MONITOR
2-WIRE SERIAL TEMPERATURE
Explanation
The device sending data to the bus.
The device receiving data from the bus.
The device which controls the bus: initiating
transfers (START), generating the clock, and
terminating transfers (STOP).
The device addressed by the master.
A unique condition signaling the beginning of a
transfer indicated by SDA falling (High-Low) while
SCL is high.
A unique condition signaling the end of a transfer
indicated by SDA rising (Low - High) while SCL is
high.
A Receiver acknowledges the receipt of each
byte with this unique condition. The Receiver
drives SDA low during SCL high of the ACK
clock-pulse. The Master provides the clock pulse
for the ACK cycle.
When the bus is idle, both SDA & SCL will
remain high.
The state of SDA must remain stable during the
High period of SCL in order for a data bit to be
considered valid. SDA only changes state while
SCL is low during normal data transfers. (See
Start and Stop conditions)