STDS75DS2E STMICROELECTRONICS [STMicroelectronics], STDS75DS2E Datasheet - Page 20

• Manufacturer Part Number: STDS75DS2E
• Description: Digital temperature sensor and thermal watchdog
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

3.3
Note:
3.4
3.4.1
3.4.2
3.4.3
20/37
Serial interface
Writing to and reading from the STDS75 registers is accomplished via the two-wire serial
interface protocol which requires that one device on the bus initiates and controls all READ
and WRITE operations. This device is called the “master” device. The master device also
generates the SCL signal which provides the clock signal for all other devices on the bus.
These other devices on the bus are called “slave” devices. The STDS75 is a slave device
(see
During operations, one data bit is transmitted per clock cycle. All operations follow a
repeating, nine-clock-cycle pattern that consists of eight bits (one byte) of transmitted data
followed by an acknowledge (ACK) or not acknowledge (NACK) from the receiving device.
There are no unused clock cycles during any operation, so there must not be any breaks in
the data stream and ACKs/NACKs during data transfers. Conversely, having too few clock
cycles can lead to incorrect operation if an inadvertent 8-bit READ from a 16-bit register
occurs.
Table 10.
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bi-
directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be
connected to a positive supply voltage via a pull-up resistor.
●
●
●
●
Accordingly, the following bus conditions have been defined (see
Bus not busy
Both data and clock lines remain High.
Start data transfer
A change in the state of the data line, from high to Low, while the clock is High, defines the
START condition.
Stop data transfer
A change in the state of the data line, from Low to High, while the clock is High, defines the
STOP condition.
MSB
Bit7
The following protocol has been defined:
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is High.
Changes in the data line, while the clock line is High, will be interpreted as control
signals.
Table
1
10). Both the master and slave devices can send and receive data on the bus.
STDS75 serial bus slave addresses
Bit6
0
Bit5
0
Bit4
1
Bit3
A2
Bit2
A1
Figure 6 on page
Bit1
A0
21):
Bit0
R/W
LSB