LM95172EWG10A NSC [National Semiconductor], LM95172EWG10A Datasheet - Page 16

• Manufacturer Part Number: LM95172EWG10A
• Manufacturer: NSC [National Semiconductor]

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When in 16-Bit resolution mode, this is the Least Significant Bit of the temperature data.
Reset Conditions: See Sections 1.1.1 through 1.1.3 for reset conditions.
One-Shot State: 8000h (-256°C)
1.7.3 Control/Status Register
(Read/Write) Pointer Address: 81h (Read); 01h (Write)
Bit <15>: Shutdown (SD) Bit. Writing a “1” to this bit and holding it high for at least the specified maximum conversion time, at the
existing temperature resolution setting, enables the Shutdown Mode. Writing a “0” to this bit restores the LM95172EWG to normal
mode.
Bit <14>: One-Shot Bit. When in shutdown mode (Bit <15> is "1"), initates a single temperature conversion and update of the
temperature register with new temperature data. Has no effect when in continuous conversion mode (i.e., when Bit <15> is "0").
Always returns a "0" when read.
Bit <13>: OVERTEMP Reset Bit. Writing a "1" to this Bit resets the OVERTEMP Status bit and, after a possible wait up to one
temperature conversion time, the OVERTEMP pin. It will always return a "0" when read.
Bit <12>: Conversion Toggle Bit. Toggles each time the Control/Status register is read if a conversion has completed since the
last read. If conversion has not been completed, the value will be the same as last read.
Bit <11>: OVERTEMP Status Bit. This Bit is "0" when OVERTEMP output is low and "1" when OVERTEMP output is high. The
OVERTEMP output is reset under the following conditions: (1) Cleared by writing a "1" to the OVERTEMP Reset Bit (Bit <13>) in
this register or (2) Measured temperature falls below the T
is set to "1", then the Bit and the pin clear until the next conversion, at which point the Bit and pin would assert again.
Bit <10>: Temperature High (T
in the programmable T
the programmed T
the status Bit remains set until it is read by the master so that the system can check the history of what caused the OVERTEMP
to assert.
Bit <9>: Temperature Low (T
in the programmable T
the programmed T
the T
OVERTEMP to assert.
Bit <8>: Data Available (DAV) Status Bit. This Bit is "0" when the temperature sensor is in the process of converting a new tem-
perature. It is "1" when the conversion is done. It is reset after each read and goes high again after one temperature conversion
is done. In one-shot mode: after initiating a temperature conversion while operating, this status Bit can be monitored to indicate
when the conversion is done. After triggering the one-shot conversion, the data in the temperature register is invalid until this Bit
is high (i.e., after completion of the first conversion).
Bit <7>: OVERTEMP Disable Bit. When set to "0" the OVERTEMP output is enabled. When set to "1" the OVERTEMP output is
disabled. This Bit also controls the OVERTEMP Status Bit (this register, Bit <11>) since that Bit reflects the state of the
OVERTEMP pin.
Bit <6>: OVERTEMP Polarity Bit. When set to "1", OVERTEMP is active-high. When "0" it is active-low.
LOW
limit, the status Bit remains set until it is read by the master so that the system can check the history of what caused the
OVERTEMP
D15
SD
Disable
HIGH
LOW
D7
HIGH
LOW
One-Shot
limit and (2) upon reading the Control/Status Register. If the temperature no longer exceeds the T
limit and (2) upon reading the Control/Status Register. If the temperature is no longer below, or equal to,
D14
register. The flag is reset to "0" when both of two conditions are met: (1) temperature is no longer below
register. The flag is reset to "0" when both of two conditions are met: (1) temperature no longer exceeds
LOW
OVERTEMP
HIGH
) Flag Bit. This Bit is set to "1" when the measured temperature falls below the T
POL
) Flag Bit. This Bit is set to "1" when the measured temperature exceeds the T
D6
OVERTEMP
Reset
D13
RES1
D5
Conversion
Toggle
D12
LOW
RES0
D4
limit. If the temperature is still above T
16
OVERTEMP
D3
Status
0
D11
reserved
D2
T
D10
HIGH
reserved
T
D1
D9
LOW
HIGH
, and OVERTEMP Reset
DAV
D8
D0
0
HIGH
LOW
limit stored
limit stored
HIGH
limit,