NX2139ACMTR MICROSEMI [Microsemi Corporation], NX2139ACMTR Datasheet - Page 16

• Manufacturer Part Number: NX2139ACMTR
• Description: SINGLE CHANNEL MOBILE PWM AND LDO CONTROLLER
• Manufacturer: MICROSEMI [Microsemi Corporation]

Here C
POSCAP, R
capacitors are chosen as LDO output capacitors, the
zero caused by output capacitor ESR is so high that
crossover frequency F
than zero caused by R
zero caused by ESR . For example, 10uF ceramic is
used as output capacitor. We select Fo=300kHz,
R
and C
than calculated value to compensate parasitic effect.
Choose R
Current Limit for LDO
LDO feedback voltage. When LDO_FB pin is below
Rev. 2.3
03/19/09
f1
=7.5kohm and select MOSFET SI4800(g
R =R
When ceramic capacitors or some low ESR bulk
Typically R
C
R
Choose R
Choose C
C =
R =
C
=14.9k
=7.5k
Current limit of LDO is achieved by sensing the
f2
f2
C
C
can be calculated as follows.
=7.5k
=0.53nF
is determined by the desired output voltage.
=
=
f1
is chosen to be 33pF. For electrolytic or
C
10 C
R
V
7.5k
20k
1.5V 0.75V
=20k
10 20uF
LDOOUT
C
C
R
2
is typically selected to be zero.
f1
C
g
C
f2
2
=1000pF.
is chosen to be 1 to 1.5 times smaller
O
m
=7.5k
V
g
0.75V
19S
REF
F
m
V
O
REF
O
300kHz 20uF
C
C
has to be chosen much higher
19S
O
and C
1+g
g
m
C
m
and much lower than
V
I
OUT
V
OUT
I
OUT
OUT
1+19S
19S
m
=19). R
1.5V
2A
1.5V
2A
C
70% of V
turn off all the channel until VCC or ENSW resets.
Power Good for LDO
up resistor is needed. Typically when softstart is
finised and LDOFB pin voltage is over 90% of V
the LDOPGOOD pin is pulled to high.
Layout Considerations
frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
the layout which are power components and small sig-
nal components. Power components usually consist of
input capacitors, high-side MOSFET, low-side
MOSFET, inductor and output capacitors. A noisy en-
vironment is generated by the power components due
to the switching power. Small signal components are
connected to sensitive pins or nodes. A multilayer lay-
out which includes power plane, ground plane and sig-
nal plane is recommended .
layer connected by wide, copper filled areas. The input
capacitor, inductor, output capacitor and the MOSFETs
should be close to each other as possible. This helps
to reduce the EMI radiated by the power loop due to
the high switching currents through them.
RMS ripple current and a high frequency decoupling
ceramic cap which usually is 1uF
cally
plane connection is a must.
as to the load as possible and plane connection is re-
quired.
the high-side MOSFET need to be connected thru a
plane and as close as possible. A snubber needs to be
placed as close to this junction as possible.
Power good output is open drain output, a pull
The layout is very important when designing high
There are two sets of components considered in
Layout guidelines:
1. First put all the power components in the top
2. Low ESR capacitor which can handle input
3. The output capacitors should be placed as close
4. Drain of the low-side MOSFET and source of
touching the drain pin of the upper MOSFET, a
REF
, the IC goes into latch mode. The IC will
need to be practi-
NX2139A
REF
16
,