IR3895MPBF IRF [International Rectifier], IR3895MPBF Datasheet
IR3895MPBF
Related parts for IR3895MPBF
IR3895MPBF Summary of contents
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FEATURES Single 5V to 21V application Wide Input Voltage Range from 1.0V to 21V with external Vcc Output Voltage Range: 0.5V to 0.86* Vin Enhanced Line/Load Regulation with Feed‐Forward Programmable Switching Frequency up to 1.5MHz Internal Digital Soft‐Start/Soft‐Stop Enable input with Voltage Monitoring Capability Thermally Compensated Current Limit with robust hiccup mode over current protection Smart internal LDO to improve light load and full load efficiency External Synchronization with Smooth Clocking Enhanced Pre‐Bias Start‐Up Precision Reference Voltage (0.5V+/‐0.5%) with margining capability Vp for Tracking Applications (source/sink capability ±16A) Integrated MOSFET drivers and Bootstrap Diode Thermal Shut Down Programmable Power Good Output with tracking capability ...
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ORDERING INFORMATION IR3895 ― PBF – Lead Free TR/TR1 – Tape and Reel M – Package Type PIN DIAGRAM 5m x 6mm POWER QFN (TOP VIEW) Fb AUGUST 08, 2012 | DATA SHEET| Rev 3.1 2 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator Package M M Vref Comp Gnd Rt/SyncS_Ctrl PGood ...
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BLOCK DIAGRAM V LDO_Ref LDO Gnd - + Comp VREF Vref Vp 0.15V Fb Intl_SS Vin FAULT SOFT S_Ctrl START SSOK VREF POR Vp UVEN UVEN Enable POR POR UVcc OVER VOLTAGE OV PROTECTION Vsns Figure 3: IR3895 Simplified Block Diagram AUGUST 08, 2012 | DATA SHEET| Rev 3.1 3 16A Highly Integrated SupIRBuck ...
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PIN DESCRIPTIONS PIN # PIN NAME 1 Fb 2 Vref 3 Comp 4 Gnd 5 Rt/Sync 6 S_Ctrl 7 PGood 8 Vsns 9 Vin 10 Vcc/LDO_Out 11 PGnd 12 SW 13 PVin 14 Boot 15 Enable 16 Vp 17 Gnd ...
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ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. PVin, Vin Vcc/LDO_Out Boot SW Boot to SW S_Ctrl, PGood Other Input/Output Pins PGnd to Gnd Storage Temperature Range Junction Temperature Range ESD Classification (HBM JESD22‐A114) Moisture Sensitivity Level Note 1: Must not exceed 8V Note 2: Vcc must not exceed 7.5V for Junction Temperature between ‐10°C and ‐40°C AUGUST 08, 2012 | DATA SHEET| Rev 3.1 5 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator ‐0.3V to 25V ‐0.3V to 8V (Note 2) ‐0.3V to 33V ‐0.3V to 25V (DC), ‐4V to 25V (AC, 100ns) ‐0.3V to VCC + 0.3V (Note 1) ‐0.3V to VCC + 0.3V (Note 1) ‐0.3V to +3.9V ‐0.3V to +0.3V ‐55°C to 150°C ...
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ELECTRICAL SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN Input Voltage Range* Input Voltage Range** Supply Voltage Range*** Supply Voltage Range Output Voltage Range Output Current Range Switching Frequency Operating Junction Temperature *Maximum SW node voltage should not exceed 25V. **For internally biased single rail operation. *** Vcc/LDO_out can be connected to an external regulated supply. If so, the Vin input should be connected to Vcc/LDO_out pin. ELECTRICAL CHARACTERISTICS Unless otherwise specified, these specifications apply over, 6.8V < Vin = PVin < 21V, Vref = 0.5V in 0°C < T Typical values are specified at T = 25°C. a PARAMETER Power Stage Power Losses Top Switch Bottom Switch Bootstrap Diode Forward Voltage SW Leakage Current Dead Band Time Supply Current Vin Supply Current (standby) Vin Supply Current (dynamic) VCC LDO Output Output Voltage VCC Dropout Short Circuit Current AUGUST 08, 2012 | DATA SHEET| Rev 3.1 6 16A Highly Integrated SupIRBuck ...
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Single‐Input Voltage, Synchronous Buck Regulator PARAMETER Zero‐crossing Comparator Delay Zero‐crossing Comparator Offset Oscillator Rt Voltage Frequency Range Ramp Amplitude Ramp Offset Ramp(os) Min Pulse Width Tmin(ctrl) Max Duty Cycle Fixed Off Time Sync Frequency Range Sync Pulse Duration Sync Level Threshold Error Amplifier Input Offset Voltage Vos_Vref Input Bias Current Input Bias Current Sink Current Isink(E/A) Source Current Isource(E/A) Slew Rate Gain‐Bandwidth Product DC Gain Maximum output Voltage Vmax(E/A) Minimum output Voltage Vmin(E/A) Common Mode input Voltage Reference Voltage Feedback Voltage AUGUST 08, 2012 | DATA SHEET| Rev 3.1 7 ...
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Single‐Input Voltage, Synchronous Buck Regulator PARAMETER Accuracy Vref Margining Voltage Vref_marg Sink Current Isink_Vref Source Current Isrc_Vref Vref Comparator Threshold Vref_disable Vref_enable Soft Start/Stop Soft Start Ramp Rate (SS_start) Soft Start Ramp Rate (SS_stop) S_Ctrl Threshold Power Good PGood Turn on Threshold PGood Lower Turn off Threshold VPG(lower) PGood Turn on Delay VPG(on)_Dly Vsns Rising, see VPG(on) PGood Upper Turn off Threshold VPG(upper) PGood Comparator Delay VPG(comp)_ PGood Voltage Low PG(voltage) Tracker Comparator Upper VPG(tracker Threshold Tracker Comparator Lower VPG(tracker Threshold ...
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PARAMETER Enable‐Stop‐Threshold Enable_UVL O_Stop Enable Leakage Current Over‐Voltage Protection OVP Trip Threshold OVP Comparator Delay Over‐Current Protection Current Limit Hiccup Blanking Time Tblk_Hiccup Over‐Temperature Protection Thermal Shutdown Threshold Hysteresis Note 3: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production. Note 4: Guaranteed by design but not tested in production. AUGUST 08, 2012 | DATA SHEET| Rev 3.1 9 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator SYMBOL CONDITIONS Supply ramping down Ien Enable = 3.3V OVP_Vth Vsns Rising, 0.45V < Vref < 1.2V Vsns Rising, Vref < 0.1V OVP_Tdly I Tj = 25°C, Vcc = 6.4V LIMIT ...
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TYPICAL EFFICIENCY AND POWER LOSS CURVES PVin = 12V, Vcc = Internal LDO (4.4V/6.4V), Io = 0A‐16A, Fs = 600kHz, Room Temperature, No Air Flow. Note that the efficiency and power loss curves include the losses of IR3895, the inductor losses and the losses of the input and output capacitors. The table below shows the inductors used for each of the output voltages in the efficiency measurement. Vout(V) Lout(µH) 1.0 0.4 1.2 0.4 1.8 0.47 3.3 0.82 5 1.0 ...
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TYPICAL EFFICIENCY AND POWER LOSS CURVES PVin = 12V, Vcc = External 5V, Io = 0A‐16A, Fs = 600kHz, Room Temperature, No Air Flow. Note that the efficiency and power loss curves include the losses of IR3895, the inductor losses and the losses of the input and output capacitors. The table below shows the inductors used for each of the output voltages in the efficiency measurement. Vout(V) Lout(µH) 1.0 0.4 1.2 0.4 1.8 0.47 3.3 0.82 5 1.0 ...
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TYPICAL EFFICIENCY AND POWER LOSS CURVES PVin = 5.0V, Vcc = 5.0V, Io = 0A‐16A, Fs = 600kHz, Room Temperature, No Air Flow. Note that the efficiency and power loss curves include the losses of IR3895, the inductor losses and the losses of the input and output capacitors. The table below shows the inductors used for each of the output voltages in the efficiency measurement. Vout(V) 1.0 1.2 1.8 AUGUST 08, 2012 | DATA SHEET| Rev 3.1 12 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator ...
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THERMAL DERATING CURVES Measurement done on Evaluation board of IRDC3895.PCB is 4 layer board with 2 oz Copper, FR4 material, size 2.23"x2" PVin = 12V, Vout=1.2V, Vcc = Internal LDO (6.4V), Fs = 600kHz PVin = 12V, Vout=3.3V, Vcc = Internal LDO (6.4V), Fs = 600kHz AUGUST 08, 2012 | DATA SHEET| Rev 3.1 13 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - ...
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RDSON OF MOSFETS OVER TEMPERATURE AT V RDSON OF MOSFETS OVER TEMPERATURE AT Vcc=5.0V AUGUST 08, 2012 | DATA SHEET| Rev 3.1 14 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator - ...
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TYPICAL OPERATING CHARACTERISTICS (‐40°C TO +125°C) AUGUST 08, 2012 | DATA SHEET| Rev 3.1 15 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator ...
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TYPICAL OPERATING CHARACTERISTICS (‐40°C TO +125°C) Note: See Over Current Protection Section AUGUST 08, 2012 | DATA SHEET| Rev 3.1 16 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator Note: See Over Current Protection Section PD‐97746 IR3895 ...
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THEORY OF OPERATION DESCRIPTION The IR3895 uses a PWM voltage mode control scheme with external compensation to provide good noise immunity and maximum flexibility in selecting inductor values and capacitor types. The switching frequency is programmable from 300 kHz to 1.5MHz and provides the capability of optimizing the design in terms of size and performance. IR3895 provides precisely regulated output voltage programmed via two external resistors from 0.5V to 0.86*Vin. The IR3895 operates with an internal bias supply (LDO) which is connected to the Vcc/LDO_out pin. This allows operation with single supply. The bias voltage is variable according to load condition. If the output load current is less than half of the peak‐to‐peak inductor current, a lower bias voltage, 4.4V, is used as the internal gate drive voltage; otherwise, a higher voltage, 6.4V, is used. This feature helps the converter to reduce power losses. The IC can also be operated with an external supply from 4.5 to 7.5V, allowing an extended operating input voltage (PVin) range from 1.0V to 21V. For using the internal LDO supply, the Vin pin should be connected to PVin pin. If an external supply is used, it should be connected to Vcc/LDO_Out pin and the Vin pin should be shorted to Vcc/LDO_Out pin. The device utilizes the on‐resistance of the low side MOSFET (sync FET) for over current protection. This method enhances the converter’s efficiency and reduces cost by eliminating the need for external current sense resistor. IR3895 includes two low R MOSFETs using IR’s HEXFET ds(on) technology. These are specifically designed for high efficiency applications. UNDER‐VOLTAGE LOCKOUT AND POR The under‐voltage lockout circuit monitors the voltage of ...
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Single‐Input Voltage, Synchronous Buck Regulator Pvin(12V) Enable >1.2V Intl_SS Figure 5a: Recommended startup for Normal operation Pvin (12V) Vcc Enable > Figure 5b: Recommended startup for sequencing operation (ratiometric or simultaneous) Pvin (12V) Vcc Vref=0 Enable > Figure 5c: Recommended startup for memory tracking operation (Vtt‐DDR) AUGUST 08, 2012 | DATA SHEET| Rev 3.1 18 16A Highly Integrated SupIRBuck Figure 5a shows the recommended start‐up sequence for the normal (non‐tracking, non‐sequencing) operation of IR3895, when Enable is used as a logic input. Figure 5b shows the recommended startup sequence for sequenced operation of IR3895 with Enable used as logic input. Figure Vcc ...
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SOFT‐START IR3895 has an internal digital soft‐start to control the output voltage rise and to limit the current surge at the start‐up. To ensure correct start‐up, the soft‐start sequence initiates when the Enable and Vcc rise above their UVLO thresholds and generate the Power On Ready (POR) signal. The internal soft‐start (Intl_SS) signal linearly rises with the rate of 0.2mV/µs from 0V to 1.5V. Figure 7 shows the waveforms during soft start (also refer to Fig. 20). The normal Vout start up time is fixed, and is equal to: 0.65V-0.15V T 2.5ms start 0.2mV/ s During the soft start the over‐current protection (OCP) and over‐voltage protection (OVP) is enabled to protect the device for any short circuit or over voltage condition. POR 1.5V 0.65V 0.15V Intl_SS Vout Figure 7: Theoretical operation waveforms during soft‐start (non tracking / non sequencing) OPERATING FREQUENCY The switching frequency can be programmed between ...
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I (2) OCP LIMIT 2 I = DC current limit hiccup point OCP I = Current limit Valley Point LIMIT ΔI=Inductor ripple current Figure 8: Timing Diagram for Current Limit Hiccup THERMAL SHUTDOWN Temperature sensing is provided inside IR3895. The trip o threshold is typically set to 145 C. When trip threshold is exceeded, thermal shutdown turns off both MOSFETs and resets the internal soft start. Automatic restart is initiated when the sensed temperature drops within the operating range. There is o a 20 C hysteresis in the thermal shutdown threshold. EXTERNAL SYNCHRONIZATION IR3895 incorporates an internal phase lock loop (PLL) circuit which enables synchronization of the internal oscillator to an external clock. This function is important to avoid sub‐harmonic oscillations due to beat frequency for embedded systems when multiple point‐of‐load (POL) regulators are used. A multi‐function pin, Rt/Sync, is used to connect the external clock. If the external clock is ...
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Feed‐Forward Feed‐Forward (F.F.) is an important feature, because it can keep the converter stable and preserve its load transient performance when Vin varies in a large range. In IR3895, F.F. function is enabled when Vin pin is connected to PVin pin. In this case, the internal low dropout (LDO) regulator is used. The PWM ramp amplitude (Vramp) is proportionally changed with Vin to maintain Vin/Vramp almost constant throughout Vin variation range (as shown in Fig. 10). Thus, the control loop bandwidth and phase margin can be maintained constant. Feed‐forward function can also minimize impact on output voltage from fast Vin change. The maximum Vin slew rate is within 1V/µs. If an external bias voltage is used as Vcc, Vin pin should be connected to Vcc/LDO_out pin instead of PVin pin. Then the F.F. function is disabled. A re‐calculation of control loop parameters is needed for re‐compensation. Figure 10: Timing Diagram for Feed‐Forward (F.F.) Function SMART LOW DROPOUT REGULATOR (LDO) IR3895 has an integrated low dropout (LDO) regulator which can provide gate drive voltage for both drivers. In order to improve overall efficiency over the whole load range, LDO voltage is set to 6.4V (typical.) at mid‐ or heavy load condition to reduce Rds(on) and thus MOSFET conduction loss; and it is reduced to 4.4 (typical.) at light load condition to reduce gate drive loss. The smart LDO can select its output voltage according to the load condition by sensing switch node (SW) voltage. At light load condition when part of the inductor current flows in the reverse direction (DCM=1), V falling edge in a switching cycle. If this case happens for consecutive 256 switching cycles, the smart LDO reduces its output to 4.4V. If in any one of the 256 cycles, Vsw < 0 on LDrv falling edge, the counter is reset and LDO voltage doesn’t change. On the other hand, if Vsw < 0 on LDrv falling edge (DCM=0) , LDO output is increased to 6.4V. A hysteresis band is added to Vsw comparison to avoid AUGUST 08, 2012 | DATA SHEET| Rev 3.1 21 ...
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Therefore, in normal operating condition, after Enable goes high, the internal soft‐start (Intl_SS) ramps up the output voltage until Vfb (voltage of feedback/Fb pin) reaches about 0.5V. Then Vref takes over and the output voltage is regulated.. Tracking‐mode operation is achieved by connecting Vref to GND. Then, while Vp=0, Enable is taken above its threshold so that the soft‐start circuit generates Intl_SS signal. After the Intl_SS signal reaches the final value (refer to Fig.5c) , ramping up the Vp input will ramp up the output voltage. In tracking mode, Vfb always follows Vp which means Vout is always proportional to Vp voltage (typical for DDR/Vtt rail applications). The effective Vp variation range is 0V~1.2V. In sequencing mode of operation (simultaneous or ratiometric), Vref is left floating and Vp is kept to ground level until Intl_SS signal reaches the final value. Then Vp is ramped up and Vfb follows Vp. When Vp>0.5V the error‐ amplifier switches to Vref and the output voltage is regulated with Vref.The final Vp voltage after sequencing startup should between 0.7V ~ 3.3V. AUGUST 08, 2012 | DATA SHEET| Rev 3.1 22 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator 6.8 V ...
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Vcc Vref=0V (slave) Enable (slave) 1.2V Soft Start (slave) Vo2 (slave) (a) (b) Vo2 (slave) Figure 14: Typical waveforms in tracking mode of operation: (a) simultaneous, (b) ratiometric ABLE EQUIRED ONDITIONS FOR IMULTANEOUS 12) RACKING AND EQUENCING IG Operating Vref Mode (Slave) ...
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Figure 17: Vp Sequence and Vref Margin OVER‐VOLTAGE PROTECTION (OVP) Over‐voltage protection in IR3895 is achieved by comparing sense pin voltage Vsns to a pre‐set threshold. In non‐tracking mode, OVP threshold can be set at 1.2*Vref; in tracking mode, it can be at 1.2*Vp. When Vsns exceeds the over voltage threshold, an over voltage trip signal asserts after 2us (typical.) delay. Then the high side drive signal HDrv is turned off immediately, PGood flags low. The low side drive signal is kept on until the Vsns voltage drops below the threshold. After that, HDrv is latched off until a reset performed by cycling either Vcc or Enable. Vsns voltage is set by the voltage divider connected to the output and it can be programmed externally. Figure 18 shows the timing diagram for OVP in non‐tracking mode. Figure 18: Timing Diagram for OVP in non‐tracking mode AUGUST 08, 2012 | DATA SHEET| Rev 3.1 24 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator SOFT‐STOP (S_CTRL) Soft‐stop function can make output voltage discharge gradually. To enable this function, S_Ctrl is kept low first when EN goes high. Then S_Ctrl is pulled high to cross the logic level threshold (typical 2V), the internal soft‐start ramp is initiated. So Vo follows Intl_SS to ramp up until it reaches its steady state. In soft‐stop process, S_Ctrl needs to be pulled low before EN goes low. After S_Ctrl goes below its threshold, a decreasing ramp is generated at Intl_SS with the same slope as in soft‐start ramp. Vo follows this ramp to discharge softly until shutdown completely. Figure 19 shows the timing diagram of S_Ctrl controlled soft‐start and soft‐stop. If the falling edge of Enable signal asserts before S_Ctrl ...
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MINIMUM ON TIME CONSIDERATIONS The minimum ON time is the shortest amount of time for Ctrl FET to be reliably turned on. This is very critical parameter for low duty cycle, high frequency applications. Conventional approach limits the pulse width to prevent noise, jitter and pulse skipping. This results to lower closed loop bandwidth. IR has developed a proprietary scheme to improve and enhance minimum pulse width which utilizes the benefits of voltage mode control scheme with higher switching frequency, wider conversion ratio and higher closed loop bandwidth, the latter results in reduction of output capacitors. Any design or application using IR3895 must ensure operation with a pulse width that is higher than this minimum on‐time and preferably higher than 60 ns. This is necessary for the circuit to operate without jitter and pulse‐skipping, which can cause high inductor current ripple and high output voltage ripple. out t on In any application that uses IR3895, the following condition must be satisfied: ...
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DESIGN EXAMPLE The following example is a typical application for IR3895. The application circuit is shown in Fig.28. Ripple Voltage= 1 Δ 50% load transient for = o ...
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V . However, if the value of C1 is appropriately chosen, in the voltage V across C1 remains approximately c unchanged and the voltage at the Boot pin becomes: Boot Figure 24: Bootstrap circuit to generate Vc voltage A bootstrap capacitor of value 0.1uF is suitable for most applications. Input Capacitor Selection The ripple current generated during the on time of the control FET should be provided by the input capacitor. The RMS value of this ripple is expressed by: RMS o ...
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Output Capacitor Selection The voltage ripple and transient requirements determine the output capacitors type and values. The criteria is normally based on the value of the Effective Series Resistance (ESR). However the actual capacitance value and the Equivalent Series Inductance (ESL) are other contributing components. These components can be described as: ESR ( ) o ESL ( ) ESR * o ESR ( ...
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The ESR zero of the output capacitor is expressed as follows: 1 F ESR 2 π * ESR ain ( ( ...
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V Z OUT REF Gain (dB) |H(s Figure 27: Type III Compensation network and its asymptotic gain plot Again, the transfer function is given by: ...
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... The small signal value may be obtained from the manufacturer’s datasheets, design tools or SPICE models. Alternatively, they may also be inferred from measuring the power stage transfer function of the converter and measuring the double pole frequency F and ...
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... Thick Film, 0603,1/10W,1% Panasonic PQFN 5x6mm PD‐97746 IR3895 Part Number EEV-FK1E331P TDK C3216X5R1E106M Murata GRM188R71E104KA01B Murata GRM1885C1E102JA01D Murata GRM188R71H332KA01B Murata GRM1885C1H221JA01D TDK C2012X5R0J476M TDK C1608X5R1C225M Murata GRM188R71E103KA01J Murata GRM188R61E105KA12D Vitec 59PR9875N ERJ-3EKF1781V ERJ-3EKF4021V ERJ-3EKF2871V ERJ-3EKF1000V ERJ-3EKF3922V ERJ-3EKF4992V ERJ-3EKF7551V IR IR3895MPBF ...
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... 3.32k 2.2nF 0.1uF R5 R4 3.32k 100 Co=6X47uF R6 R3 3.32k Part Number EEV-FK1E331P TDK C3216X5R1E106M Murata GRM188R71E104KA01B Murata GRM1885C1E102JA01D Murata GRM188R71H222KA01B TDK C1608C0G1H181J TDK C2012X5R0J476M TDK C1608X5R1C225M TDK C1608X7R1H153K Murata GRM188R61E105KA12D Vitec 59PR9874N ERJ-3EKF2491V ERJ-3EKF3321V ERJ-3EKF1000V ERJ-3EKF3922V ERJ-3EKF4992V IR IR3895MPBF ...
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TYPICAL OPERATING WAVEFORMS PVin = 12V, Vo = 1.2V, Iout = 0‐16A, Room Temperature, No Air flow Figure 30: Start up at 16A Load, Ch :Vout, Ch :Vin, Good Figure 32: Start up with Pre Bias voltage, 0A Load, Ch :V Figure 34: Inductor node at 16A load, Ch AUGUST 08, 2012 | DATA SHEET| Rev 3.1 34 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator :Enable ...
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TYPICAL OPERATING WAVEFORMS Vin = 12V, Vo = 1.2V, Iout = 0‐16A, Room Temperature, No Air Flow Figure 36: Turn on at No Load showing Vcc level Ch1‐Vout, Ch2‐Vin, Ch3‐Vcc,Ch4‐Inductor current Figure 38: Transient Response, 8A to 16A step at 2.5A/uSec slew rate, AUGUST 08, 2012 | DATA SHEET| Rev 3.1 35 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator Figure 37: Turn on at Full Load showing Vcc level Ch1‐Vout, Ch2‐Vin,Ch3‐Vcc,Ch4‐Inductor current ...
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TYPICAL OPERATING WAVEFORMS PVin = 12V, Vo = 1.2V, Iout = 0‐16A, Room Temperature, No Air flow Figure 39: Feed forward for Vin change from 6.8 to 16V, , Ch :V 1 out 2 in Figure 41: External frequency synchronization to 800kHz from free running 600kHz, o, Voltage,Ch :SW Node Voltage 3 ...
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TYPICAL OPERATING WAVEFORMS Vin = 12V, Vo = 1.2V, Iout = 0‐16A, Room Temperature, No Air Flow Figure 45: Bode Plot at 16A load shows a bandwidth of 95.2kHz and phase margin of 54.5° AUGUST 08, 2012 | DATA SHEET| Rev 3.1 37 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator Figure 46: Thermal Image of the Board at 16A Load, Test Point 1 is IR3895, Test Point 2 is inductor PD‐97746 IR3895 ...
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LAYOUT RECOMMENDATIONS The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Make the connections for the power components in the top layer with wide, copper filled areas or polygons. In general, it is desirable to make proper use of power planes and polygons for power distribution and heat dissipation. The inductor, output capacitors and the IR3899 should be as close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place the input capacitor directly at the PVin pin of IR3899. The feedback part of the system should be kept away from the inductor and other noise sources. Compensation parts should be placed as close as possible to the Comp pin Resistor ...
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Single point connection between AGND & PGND, should be close to the SupIRBuck kept away from noise sources Figure 47b: IRDC3895 Demo board Layout Considerations – Bottom Layer Analog ground plane Figure 47c: IRDC3895 Demo board Layout Considerations – Mid Layer 1 ...
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PCB METAL AND COMPONENT PLACEMENT Evaluations have shown that the best overall performance is achieved using the substrate/PCB layout as shown in following Figures. PQFN devices should be placed to an accuracy of 0.050mm on both X and Y axes. Self‐centering behavior is highly dependent on solders Figure 48: PCB Metal Pad Sizing and Spacing (all dimensions in mm) * Contact International Rectifier to receive an electronic PCB Library file in your preferred format AUGUST 08, 2012 | DATA SHEET| Rev 3.1 40 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator and processes and experiments should be run to confirm the limits of self‐centering on specific processes. For further information, please refer to “SupIRBuck™ Multi‐Chip Module (MCM) Power Quad Flat No‐Lead (PQFN) Board Mounting Application Note.” (AN1132) PD‐97746 IR3895 ...
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SOLDER RESIST IR recommends that the larger Power or Land Area pads are Solder Mask Defined (SMD.) This allows the underlying Copper traces to be as large as possible, which helps in terms of current carrying capability and device cooling capability. When using SMD pads, the underlying copper traces should be at least 0.05mm larger (on each edge) than the Solder Mask window, in order to accommodate any layer to layer misalignment. (i.e. 0.1mm in X & Y.) * Contact International Rectifier to receive an electronic PCB Library file in your preferred format AUGUST 08, 2012 | DATA SHEET| Rev 3.1 41 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator However, for the smaller Signal type leads around the edge of the device, IR recommends that these are Non Solder Mask Defined or Copper Defined. When using NSMD pads, the Solder Resist Window should be larger than the Copper Pad by at least 0.025mm on each edge, (i.e. 0.05mm in X&Y,) in order to accommodate any layer to layer misalignment. Ensure that the solder resist in‐between the smaller signal lead areas are at least 0.15mm wide, due to the high x/y aspect ratio of the solder mask strip. Figure 49: Solder resist PD‐97746 IR3895 ...
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STENCIL DESIGN Stencils for PQFN can be used with thicknesses of 0.100‐0.250mm (0.004‐0.010"). Stencils thinner than 0.100mm are unsuitable because they deposit insufficient solder paste to make good solder joints with the ground pad; high reductions sometimes create similar problems. Stencils in the range of 0.125mm‐0.200mm (0.005‐0.008"), with suitable reductions, give the best results. * Contact International Rectifier to receive an electronic PCB Library file in your preferred format AUGUST 08, 2012 | DATA SHEET| Rev 3.1 42 16A Highly Integrated SupIRBuck Single‐Input Voltage, Synchronous Buck Regulator Evaluations have shown that the best overall performance is achieved using the stencil design shown in following Figure. This design is for a stencil thickness of 0.127mm (0.005"). The reduction should be adjusted for stencils of other thicknesses. Figure 50: Stencil Pad Spacing (all dimensions in mm) PD‐97746 IR3895 ...
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Single‐Input Voltage, Synchronous Buck Regulator MARKING INFORMATION MILIMITERS DIM MIN MAX A 0.800 1.000 A1 0.000 0.050 b 0.375 0.475 b1 0.250 0.350 c 0.203 REF. D 5.000 BASIC E 6.000 BASIC e 1.033 BASIC e1 0.650 BASIC e2 0.852 BASIC IR WORLD HEADQUARTERS: ...