DSPIC30F MICROCHIP [Microchip Technology], DSPIC30F Datasheet - Page 55

• Manufacturer Part Number: DSPIC30F
• Description: General Purpose and Sensor Families High-Performance Digital Signal Controllers
• Manufacturer: MICROCHIP [Microchip Technology]

4.4.3
Modulo addressing can be applied to the effective
address (EA) calculation associated with any W regis-
ter. It is important to realize that the address bound-
aries check for addresses less than, or greater than the
upper (for incrementing buffers), and lower (for decre-
menting buffers) boundary addresses (not just equal
to). Address changes may, therefore, jump over bound-
aries and still be adjusted correctly (see Section 4.4.4
for restrictions).
4.4.4
For an incrementing buffer, the circular buffer start
address (lower boundary) is arbitrary but must be at a
‘zero’ power-of-two boundary (see Section 4.4.1). For
a decrementing buffer, the circular buffer end address
is arbitrary but must be at a ‘ones’ boundary.
There are no restrictions regarding how much an EA
calculation can exceed the address boundary being
checked and still be successfully corrected.
Once
addresses into a buffer should not be changed.
Although all EAs will continue to be generated cor-
rectly, irrespective of offset sign, only one address
boundary is checked for each type of buffer. Thus, if a
buffer is set up to be an incrementing buffer by choos-
ing an appropriate starting address, then correction of
the effective address will be performed by the AGU at
the upper address boundary, but no address correction
will occur if the EA crosses the lower address bound-
ary. Similarly, for a decrementing boundary, address
correction will be performed by the AGU at the lower
address boundary, but no address correction will take
place if the EA crosses the upper address boundary.
The circular buffer pointer may be freely modified in
both directions without a possibility of out-of-range
address access only when the start address satisfies
the condition for an incrementing buffer (last ‘N’ bits are
zeroes) and the end address satisfies the condition for
a decrementing buffer (last ‘N’ bits are ones). Thus, the
modulo addressing capability is truly bidirectional only
for modulo-2 length buffers.
 2004 Microchip Technology Inc.
Note:
configured,
MODULO ADDRESSING
APPLICABILITY
The modulo corrected effective address is
written back to the register only when Pre-
Modify or Post-Modify Addressing mode is
used to compute the effective address.
When an address offset (e.g., [W7+W2]) is
used, modulo address correction is per-
formed but the contents of the register
remain unchanged.
MODULO ADDRESSING
RESTRICTIONS
the
direction
of
successive
Preliminary
4.5
Bit-reversed addressing is intended to simplify data re-
ordering for radix-2 FFT algorithms. It is supported by
the X WAGU only (i.e., for data writes only).
The modifier, which may be a constant value or register
contents, is regarded as having its bit order reversed. The
address source and destination are kept in normal order.
Thus, the only operand requiring reversal is the modifier.
4.5.1
Bit-reversed addressing is enabled when:
1.
2.
3.
If the length of a bit-reversed buffer is M = 2
then the last ‘N’ bits of the data buffer start address
must be zeros.
XB<14:0> is the bit-reversed address modifier or ‘pivot
point’ which is typically a constant. In the case of an
FFT computation, its value is equal to half of the FFT
data buffer size.
When enabled, bit-reversed addressing will only be
executed for register indirect with pre-increment or
post-increment addressing and word sized data writes.
It will not function for any other Addressing mode or for
byte sized data, and normal addresses will be gener-
ated instead. When bit-reversed addressing is active,
the W address pointer will always be added to the
address modifier (XB) and the offset associated with
the Register Indirect Addressing mode will be ignored.
In addition, as word sized data is a requirement, the LS
bit of the EA is ignored (and always clear).
If bit-reversed addressing has already been enabled by
setting the BREN (XBREV<15>) bit, then a write to the
XBREV register should not be immediately followed by
an indirect read operation using the W register that has
been designated as the bit-reversed pointer.
Note:
Note:
BWM (W register selection) in the MODCON
register is any value other than ‘15’ (the stack
cannot
addressing) and
the BREN bit is set in the XBREV register and
the Addressing mode used is Register Indirect
with Pre-Increment or Post-Increment.
Bit-Reversed Addressing
BIT-REVERSED ADDRESSING
IMPLEMENTATION
All bit-reversed EA calculations assume
word sized data (LS bit of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
Modulo
addressing should not be enabled together.
In the event that the user attempts to do
this, bit-reversed addressing will assume
priority when active for the X WAGU, and X
WAGU modulo addressing will be disabled.
However, modulo addressing will continue
to function in the X RAGU.
be
accessed
addressing
dsPIC30F
using
and
DS70083G-page 53
bit-reversed
bit-reversed
N
bytes,