PIC24FJ128GA MICROCHIP [Microchip Technology], PIC24FJ128GA Datasheet - Page 120

• Manufacturer Part Number: PIC24FJ128GA
• Description: General Purpose, 16-Bit Flash Microcontrollers
• Manufacturer: MICROCHIP [Microchip Technology]

PIC24FJ128GA FAMILY
REGISTER 14-2:
DS39747C-page 118
Upper Byte:
bit 15
bit 15-13 Unimplemented: Read as ‘0’
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4-2
bit 1-0
U-0
—
DISSCK: Disable SCKx pin bit (SPI Master modes only)
1 = Internal SPI clock is disabled, pin functions as I/O
0 = Internal SPI clock is enabled
DISSDO: Disable SDOx pin bit
1 = SDOx pin is not used by module; pin functions as I/O
0 = SDOx pin is controlled by the module
MODE16: Word/Byte Communication Select bit
1 = Communication is word-wide (16 bits)
0 = Communication is byte-wide (8 bits)
SMP: SPIx Data Input Sample Phase bit
Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
Slave mode:
SMP must be cleared when SPIx is used in Slave mode.
CKE: SPIx Clock Edge Select bit
1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6)
0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6)
SSEN: Slave Select Enable (Slave mode) bit
1 = SSx pin used for Slave mode
0 = SSx pin not used by module. Pin controlled by port function.
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
MSTEN: Master Mode Enable bit
1 = Master mode
0 = Slave mode
SPRE2:SPRE0: Secondary Prescale (Master mode) bits
111 = Secondary prescale 1:1
110 = Secondary prescale 2:1
...
000 = Secondary prescale 8:1
PPRE1:PPRE0: Primary Prescale (Master mode) bits
11 = Primary prescale 1:1
10 = Primary prescale 4:1
01 = Primary prescale 16:1
00 = Primary prescale 64:1
Legend:
R = Readable bit
-n = Value at POR
Note:
U-0
—
Lower Byte:
bit 7
R/W-0
SSEN
SPI
The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the
Framed SPI modes (FRMEN = 1).
X
CON1: SPIx CONTROL REGISTER 1
U-0
—
R/W-0
CKP
DISSCK
R/W-0
W = Writable bit
‘1’ = Bit is set
MSTEN
R/W-0
Preliminary
DISSDO
R/W-0
SPRE2
R/W-0
MODE16
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SPRE1
R/W-0
R/W-0
SMP
SPRE0
R/W-0
© 2006 Microchip Technology Inc.
R/W-0
CKE
x = Bit is unknown
bit 8
PPRE1
R/W-0
PPRE0
R/W-0
bit 0