DSPIC30F2011 MICROCHIP [Microchip Technology], DSPIC30F2011 Datasheet - Page 201

• Manufacturer Part Number: DSPIC30F2011
• Description: High-Performance Digital Signal Controllers
• Manufacturer: MICROCHIP [Microchip Technology]

Timing Diagrams
Timing Diagrams and Specifications
Timing Diagrams.See Timing Characteristics
Timing Requirements
Timing Specifications
Trap Vectors ....................................................................... 67
© 2005 Microchip Technology Inc.
Type A, B and C Timer External Clock ..................... 165
Watchdog Timer........................................................ 163
PWM Output ............................................................... 87
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
DC Characteristics - Internal RC Accuracy............... 159
A/D Conversion
Bandgap Start-up Time............................................. 165
Brown-out Reset ....................................................... 164
CAN Module I/O........................................................ 182
CLKOUT and I/O....................................................... 162
DCI Module
External Clock........................................................... 158
I
I
Input Capture ............................................................ 168
Oscillator Start-up Timer ........................................... 164
Output Compare Module........................................... 168
Power-up Timer ........................................................ 164
Reset......................................................................... 164
Simple OC/PWM Mode............................................. 169
SPI Module
Type A Timer External Clock .................................... 166
Type B Timer External Clock .................................... 167
Type C Timer External Clock .................................... 167
Watchdog Timer........................................................ 164
PLL Clock.................................................................. 159
2
2
C Bus Data (Master Mode)..................................... 179
C Bus Data (Slave Mode)....................................... 181
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
Low-speed ........................................................ 186
AC-Link Mode ................................................... 172
Multichannel, I
Master Mode (CKE = 0) .................................... 173
Master Mode (CKE = 1) .................................... 174
Slave Mode (CKE = 0) ...................................... 175
Slave Mode (CKE = 1) ...................................... 177
2
S Modes ................................... 171
DD
).......................................... 124
DD
DD
), Case 1...................... 124
), Case 2...................... 124
dsPIC30F2011/2012/3012/3013
Preliminary
U
UART Module
UART Operation
Unit ID Locations .............................................................. 117
Universal Asynchronous Receiver Transmitter
W
Wake-up from Sleep ......................................................... 117
Wake-up from Sleep and Idle ............................................. 68
Watchdog Timer
Watchdog Timer (WDT)............................................ 117, 127
WWW Address ................................................................. 201
WWW, On-Line Support ....................................................... 7
Address Detect Mode ............................................... 105
Auto Baud Support ................................................... 106
Baud Rate Generator ............................................... 105
Enabling and Setting Up........................................... 103
Framing Error (FERR) .............................................. 105
Idle Status................................................................. 105
Loopback Mode ........................................................ 105
Operation During CPU Sleep and Idle Modes.......... 106
Overview................................................................... 101
Parity Error (PERR) .................................................. 105
Receive Break .......................................................... 105
Receive Buffer (UxRXB)........................................... 104
Receive Buffer Overrun Error (OERR Bit) ................ 104
Receive Interrupt ...................................................... 104
Receiving Data ......................................................... 104
Receiving in 8-bit or 9-bit Data Mode ....................... 104
Reception Error Handling ......................................... 104
Transmit Break ......................................................... 104
Transmit Buffer (UxTXB) .......................................... 103
Transmit Interrupt ..................................................... 104
Transmitting Data ..................................................... 103
Transmitting in 8-bit Data Mode ............................... 103
Transmitting in 9-bit Data Mode ............................... 103
UART1 Register Map ............................................... 107
UART2 Register Map ............................................... 107
Idle Mode.................................................................. 106
Sleep Mode .............................................................. 106
(UART) Module......................................................... 101
Timing Characteristics .............................................. 163
Timing Requirements ............................................... 164
Enabling and Disabling............................................. 127
Operation.................................................................. 127
DS70139C-page 199