ATXMEGA128B3-AU ATMEL [ATMEL Corporation], ATXMEGA128B3-AU Datasheet - Page 41

• Manufacturer Part Number: ATXMEGA128B3-AU
• Description: 8/16-bit Atmel XMEGA B3 Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

21. USB – Universal Serial Bus Interface
21.1
21.2
8074B–AVR–02/12
Features
Overview
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The USB module is a USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant
interface.
The USB supports 16 endpoint addresses. All endpoint addresses have one input and one out-
put endpoint, for a total of 31 configurable endpoints and one control endpoint. Each endpoint
address is fully configurable and can be configured for any of the four transfer types: control,
interrupt, bulk, or isochronous. The data payload size is also selectable, and it supports data
payloads up to 1023 bytes.
No dedicated memory is allocated for or included in the USB module. Internal SRAM is used to
keep the configuration for each endpoint address and the data buffer for each endpoint. The
memory locations used for endpoint configurations and data buffers are fully configurable. The
amount of memory allocated is fully dynamic, according to the number of endpoints in use and
One USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface
Integrated on-chip USB transceiver, no external components needed
16 endpoint addresses with full endpoint flexibility for up to 31 endpoints
Endpoint address transfer type selectable to
Configurable data payload size per endpoint, up to 1023 bytes
Endpoint configuration and data buffers located in internal SRAM
Built-in direct memory access (DMA) to internal SRAM for:
Ping-pong operation for higher throughput and double buffered operation
Multipacket transfer for reduced interrupt load and software intervention
Transaction complete FIFO for workflow management when using multiple endpoints
Clock selection independent of system clock source and selection
Minimum 1.5MHz CPU clock required for low speed USB operation
Minimum 12MHz CPU clock required for full speed operation
Connection to event system
On chip debug possibilities during USB transactions
– One input endpoint per endpoint address
– One output endpoint per endpoint address
– Control transfers
– Interrupt transfers
– Bulk transfers
– Isochronous transfers
– Configurable location for endpoint configuration data
– Configurable location for each endpoint's data buffer
– Endpoint configurations
– Reading and writing endpoint data
– Input and output endpoint data buffers used in a single direction
– CPU/DMA controller can update data buffer during transfer
– Data payload exceeding maximum packet size is transferred in one continuous transfer
– No interrupts or software interaction on packet transaction level
– Tracks all completed transactions in a first-come, first-served work queue
XMEGA B3
41