AT91SAM7S128 ATMEL [ATMEL Corporation], AT91SAM7S128 Datasheet - Page 28

• Manufacturer Part Number: AT91SAM7S128
• Manufacturer: ATMEL [ATMEL Corporation]

10.6
10.7
10.8
28
Debug Unit
Periodic Interval Timer
Watchdog Timer
AT91SAM7S Series Summary
• Vectoring
• Protect Mode
• Fast Forcing
• General Interrupt Mask
• Comprises:
• Two-pin UART
• Debug Communication Channel Support
• Chip ID Registers
• 20-bit programmable counter plus 12-bit interval counter
• 12-bit key-protected Programmable Counter running on prescaled SCLK
• Provides reset or interrupt signals to the system
• Counter may be stopped while the processor is in debug state or in idle mode
– Higher priority interrupts can be served during service of lower priority interrupt
– Optimizes interrupt service routine branch and execution
– One 32-bit vector register per interrupt source
– Interrupt vector register reads the corresponding current interrupt vector
– Easy debugging by preventing automatic operations
– Permits redirecting any interrupt source on the fast interrupt
– Provides processor synchronization on events without triggering an interrupt
– One two-pin UART
– One Interface for the Debug Communication Channel (DCC) support
– One set of Chip ID Registers
– One Interface providing ICE Access Prevention
– Implemented features are compatible with the USART
– Programmable Baud Rate Generator
– Parity, Framing and Overrun Error
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
– Offers visibility of COMMRX and COMMTX signals from the ARM Processor
– Identification of the device revision, sizes of the embedded memories, set of
– Chip ID is 0x270B0940 for AT91SAM7S256 (VERSION 0)
– Chip ID is 0x270A0740 for AT91SAM7S128 (VERSION 0)
– Chip ID is 0x27090540 for AT91SAM7S64 (VERSION 0)
– Chip ID is 0x27080342 for AT91SAM7S321 (VERSION 0)
– Chip ID is 0x27080340 for AT91SAM7S32 (VERSION 0)
peripherals
6175BS–ATARM–04-Nov-05