DSPIC30F5011 MICROCHIP [Microchip Technology], DSPIC30F5011 Datasheet - Page 27

• Manufacturer Part Number: DSPIC30F5011
• Description: High-Performance Digital Signal Controllers
• Manufacturer: MICROCHIP [Microchip Technology]

FIGURE 3-5:
3.2
The core has two data spaces. The data spaces can be
considered either separate (for some DSP instruc-
tions), or as one unified linear address range (for MCU
instructions). The data spaces are accessed using two
Address Generation Units (AGUs) and separate data
paths.
 2004 Microchip Technology Inc.
Data
Space
EA
Note:
Upper Half of Data
Space is Mapped
into Program Space
BSET
MOV
MOV
MOV
Data Address Space
16
EA<15> = 0
EA<15> = 1
CORCON,#2
#0x21, W0
W0, PSVPAG
0x8200, W0
PSVPAG is an 8-bit register, containing bits <22:15> of the program space address (i.e., it defines
the page in program space to which the upper half of data space is being mapped).
DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION
15
15
; PSV bit set
; Set PSVPAG register
; Access program memory location
; using a data space access
Data Space
0x0000
0x8000
15
0xFFFF
Preliminary
Concatenation
Address
PSVPAG
0x21
3.2.1
The data space memory is split into two blocks, X and
Y data space. A key element of this architecture is that
Y space is a subset of X space, and is fully contained
within X space. In order to provide an apparent linear
addressing space, X and Y spaces have contiguous
addresses.
8
dsPIC30F5011/5013
(1)
23
23
DATA SPACE MEMORY MAP
Program Space
15
Data Read
DS70116C-page 25
0
0x108000
0x108200
0x10FFFF