P87C51RB2 PHILIPS [NXP Semiconductors], P87C51RB2 Datasheet - Page 46

• Manufacturer Part Number: P87C51RB2
• Description: 80C51 8-bit microcontroller family
• Manufacturer: PHILIPS [NXP Semiconductors]

1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all outputs = 80 pF
3. Interfacing the microcontroller to devices with float time up to 45 ns is permitted. This limited bus contention will not cause damage to port 0
4. Parts are guaranteed by design to operate down to 0 Hz.
5. Below 16 MHz this parameter is 8 t
Philips Semiconductors
AC ELECTRICAL CHARACTERISTICS (12-CLOCK MODE, 5 V 10% OPERATION)
T
NOTES:
2003 Jan 24
Symbol
1/t
t
t
t
t
t
t
t
t
t
t
t
Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
t
External Clock
t
t
t
t
Shift register
t
t
t
t
t
amb
LHLL
AVLL
LLAX
LLIV
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
AVDV
LLWL
AVWL
QVWX
WHQX
QVWH
RLAZ
WHLH
CHCX
CLCX
CLCH
CHCL
XLXL
QVXH
XHQX
XHDX
XHDV
80C51 8-bit microcontroller family
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high
speed (30/33 MHz)
CLCL
drivers.
= 0 C to +70 C or –40 C to +85 C ; V
Figure
38
34
34
34
34
34
34
34
34
34
34
34
35
36
35
35
35
35
35
35, 36
35, 36
36
36
36
35
35, 36
38
38
38
38
37
37
37
37
37
Parameter
Oscillator frequency
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
Data valid to WR high
RD low to address float
RD or WR high to ALE high
High time
Low time
Rise time
Fall time
Serial port clock cycle time
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
CLCL
– 133.
CC
8KB/16KB/32KB/64KB OTP
= 5 V 10%, V
5
SS
= 0 V
46
1,2,3,4
Limits
MIN
0
2 t
t
t
t
3 t
0
6 t
6 t
0
3 t
4 t
t
t
7 t
t
0.32 t
0.32 t
12 t
10 t
2 t
0
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
–13
–20
–10
–25
–15
–10
–8
–10
–20
–20
–15
–15
–5
–15
–25
P87C51RA2/RB2/RC2/RD2
MAX
33
4 t
3 t
t
5 t
10
5 t
2 t
8 t
9 t
3 t
0
t
t
t
5
5
10 t
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
–10
+10
– t
– t
–35
–35
–35
–35
–10
–35
–35
+15
CLCX
CHCX
–133
16 MHz Clock
MIN
117
49.5
42.5
52.5
177.5
0
355
355
0
172.5
235
37.5
47.5
432.5
52.5
750
600
110
0
MAX
215
152.5
52.5
277.5
10
277.5
115
465
527.5
202.5
0
72.5
492
Product data
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns