P87C750EBAA PHILIPS [NXP Semiconductors], P87C750EBAA Datasheet - Page 4

• Manufacturer Part Number: P87C750EBAA
• Description: 80C51 8-bit microcontroller family 1K/64 OTP ROM, low pin count
• Manufacturer: PHILIPS [NXP Semiconductors]

1. When P0.2 is at or close to 0 Volt, it may affect the internal ROM operation. We recommend that P0.2 be tied to V
Philips Semiconductors
PIN DESCRIPTIONS
NOTE:
OSCILLATOR CHARACTERISTICS
X1 and X2 are the input and output, respectively, of an inverting
amplifier which can be configured for use as an on-chip oscillator.
To drive the device from an external clock source, X1 should be
driven while X2 is left unconnected. There are no requirements on
the duty cycle of the external clock signal, because the input to the
internal clock circuitry is through a divide-by-two flip-flop. However,
minimum and maximum high and low times specified in the data
sheet must be observed.
RESET
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-up reset, the RST pin must be high long
1998 May 01
MNEMONIC
V
V
P0.0-P0.2
P1.0-P1.7
P3.0-P3.7
RST
X1
X2
SS
CC
80C51 8-bit microcontroller family
1K/64 OTP/ROM, low pin count
2k ).
SSOP
13-20
23-21
DIP/
5-1,
8-6
12
24
18
19
20
10
11
6
7
8
9
PIN NO.
15-20,
23, 24
6, 4-1,
27-25
LCC
9-7
14
28
20
23
24
13
12
11
7
8
9
TYPE
N/A
I/O
I/O
I/O
O
I
I
I
I
I
I
I
I
I
Circuit Ground Potential
Supply voltage during normal, idle, and power-down operation.
Port 0: Port 0 is a 3-bit open-drain, bidirectional port. Port 0 pins that have 1s written to them float,
and in that state can be used as high-impedance inputs. These pins are driven low if the port register
bit is written with a 0. The state of the pin can always be read from the port register by the program.
P0.0, P0.1, and P0.2 are open drain bidirectional I/O pins with the electrical characteristics listed in
the tables that follow. While these differ from “standard TTL” characteristics, they are close enough
for the pins to still be used as general-purpose I/O. Port 0 also provides alternate functions for
programming the EPROM memory as follows:
V
OE/PGM (P0.1) – Input which specifies verify mode (output enable) or the program mode.
OE/PGM = 1 output enabled (verify mode).
OE/PGM = 0 program mode.
ASEL (P0.0) – Input which indicates which bits of the EPROM address are applied to port 3.
ASEL = 0 low address byte available on port 3.
ASEL = 1 high address byte available on port 3 (only the three least significant bits are used).
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins
that are externally pulled low will source current because of the internal pull-ups. (See DC
Electrical Characteristics: I
mode and accepts as inputs the value to program into the selected address during the program
mode. Port 1 also serves the special function features of the 80C51 family as listed below:
INT0 (P1.5): External interrupt.
INT1 (P1.6): External interrupt.
T0 (P1.7): Timer 0 external input.
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins
that are externally being pulled low will source current because of the pull-ups. (See DC Electrical
Characteristics: I
be programmed (or verified). The 10-bit address is multiplexed into this port as specified by
P0.0/ASEL.
Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device.
An internal diffused resistor to V
V
the device in the programming state allowing programming address, data and V
programming or verification purposes. The RESET serial sequence must be synchronized with the
X1 input.
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits.
X1 also serves as the clock to strobe in a serial bit stream into RESET to place the device in the
programming state.
Crystal 2: Output from the inverting oscillator amplifier.
PP
CC
. After the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places
(P0.2) – Programming voltage input. (See Note 1.)
IL
). Port 3 also functions as the address input for the EPROM memory location to
IL
). Port 1 serves to output the addressed EPROM contents in the verify
4
SS
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-up, the voltage on
V
IDLE MODE
In idle mode, the CPU puts itself to sleep while all of the on-chip
peripherals stay active. The instruction to invoke the idle mode is the
last instruction executed in the normal operating mode before the
idle mode is activated. The CPU contents, the on-chip RAM, and all
of the special function registers remain intact during this mode. The
idle mode can be terminated either by any enabled interrupt (at
which time the process is picked up at the interrupt service routine
and continued), or by a hardware reset which starts the processor in
the same manner as a power-on reset.
CC
permits a power-on RESET using only an external capacitor to
and RST must come up at the same time for a proper start-up.
NAME AND FUNCTION
83C750/87C750
CC
via a small pull-up (e.g.,
PP
Product specification
to be applied for