LPC2919 PHILIPS [NXP Semiconductors], LPC2919 Datasheet
LPC2919
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LPC2919 Summary of contents
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LPC2917/19 ARM9 microcontroller with CAN and LIN Rev. 1.01 — 15 November 2007 1. Introduction 1.1 About this document This document lists detailed information about the LPC2917/19 device. It focuses on factual information like pinning, characteristics etc. Short descriptions are ...
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NXP Semiconductors 2.2 ARM968E-S processor The ARM968E general purpose 32-bit RISC processor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and ...
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NXP Semiconductors 2.4 On-chip static RAM In addition to the two 16 kB TCMs the LPC2917/19 includes two static RAM memories: one and one of 16 kB. Both may be used for code and/or data storage. Each ...
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... LPC2919FBD144 LQFP144 pitch 0.5 mm 4.1 Ordering options Table 2. Part options Type number Flash memory (kB) LPC2917FBD144 512 LPC2919FBD144 768 LPC2917_19_1 Preliminary data sheet ARM9 microcontroller with CAN and LIN RAM (kB) SMC 80 (incl TCMs) 32-bit 80 (incl TCMs) 32-bit Rev. 1.01 — 15 November 2007 ...
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NXP Semiconductors 5. Block diagram LPC2917/19 Fig 1. LPC2917/19 block diagram LPC2917_19_1 Preliminary data sheet ARM9 microcontroller with CAN and LIN ITCM ARM968E Vectored Interrupt Controller (VIC) Embedded FLASH Memory 512/768 Kb s FLASH Memory ...
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... GPIO 2, pin 23 P3.6 12 GPIO 3, pin 6 P3.7 13 GPIO 3, pin 7 P0.30 14 GPIO 0, pin 30 P0.31 15 GPIO 0, pin 31 LPC2917_19_1 Preliminary data sheet ARM9 microcontroller with CAN and LIN 1 LPC2917FBD144 LPC2919FBD144 36 144PINS Function 2 - PWM2 CAP1 UART1 TxD CAN1 TxD UART1 RxD CAN1 RxD - - - - - TIMER0 CAP0 - TIMER0 CAP1 ...
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NXP Semiconductors Table 3. LQFP144 pin assignment Symbol Pin Description Function 0 (default) Function 1 P2.24 16 GPIO 2, pin 24 P2.25 17 GPIO 2, pin 1.8 V power supply for digital core DD(CORE ground ...
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NXP Semiconductors Table 3. LQFP144 pin assignment Symbol Pin Description Function 0 (default) Function 3.3 V power supply for I/O DD(IO) P2.2 54 GPIO 2, pin 2 P2.3 55 GPIO 2, pin 3 P1.11 56 GPIO 1, ...
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NXP Semiconductors Table 3. LQFP144 pin assignment Symbol Pin Description Function 0 (default) Function 1 P0.0 93 GPIO 0, pin ground for I/O SS(IO) P0.1 95 GPIO 0, pin 1 P0.2 96 GPIO 0, pin 2 P0.3 ...
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NXP Semiconductors Table 3. LQFP144 pin assignment Symbol Pin Description Function 0 (default) Function 1 P0.18 132 GPIO 0, pin 18 P0.19 133 GPIO 0, pin 19 P3.4 134 GPIO 3, pin 4 P3.5 135 GPIO 3, pin 5 P2.18 ...
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NXP Semiconductors 7.1.3 IEEE 1149.1 interface pins (JTAG boundary-scan test) The LPC2917/19 contains boundary-scan test logic according to IEEE 1149.1, also referred to in this document as Joint Test Action Group (JTAG). The boundary-scan test pins can be used to ...
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NXP Semiconductors LPC2917/19 SYS_CLK Vectored Interrupt Controller (VIC) Embedded FLASH Memory 512 - 768 Kb FLASH Memory Controller (FMC) Modulation and Sampling Control Subsystem MSCSS_CLK Timer 0, 1 (MTMR) PWM ADC_CLK ADC 1, 2 CAN Controller ...
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NXP Semiconductors 7.2.2 Base clock and branch clock relationship The next table contains an overview of all the base blocks in the LPC2917/19 and their derived branch clocks. A short description is given of the hardware parts that are clocked ...
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NXP Semiconductors Table 7. Base clock and branch clock overview Base clock BASE_MSCSS_CLK BASE_UART_CLK BASE_SPI_CLK BASE_TMR_CLK BASE_ADC_CLK BASE_CLK_TESTSHELL [1] This clock is always on (cannot be switched off for system safety reasons) [2] In the peripheral subsystem parts of the ...
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NXP Semiconductors The flash memory has a 128-bit wide data interface and the flash controller offers two 128-bit buffer lines to improve system performance. The flash has to be programmed initially via JTAG. In-system programming must be supported by the ...
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NXP Semiconductors Both buffer lines are invalidated after: • Initialization • Configuration-register access • Data-latch reading • Index-sector reading The modes of operation are listed in Table 8. Flash read modes Synchronous timing No buffer line Single buffer line Asynchronous ...
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NXP Semiconductors Table 9. Flash sector overview Sector number [1] 15 [1] 16 [1] 17 [1] 18 [1] Availability of sector 15 to sector 18 depends on device ...
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NXP Semiconductors Remark: If the programmed number of wait-states is more than three, flash-data reading cannot be performed at full speed (i.e. with zero wait-states at the AHB bus) if speculative reading is active. 8.2 External static memory controller 8.2.1 ...
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NXP Semiconductors Table 11. External static-memory controller banks CS[2:0] 000 001 010 011 100 101 110 111 8.2.3 External static-memory controller pin description The external static-memory controller module in the LPC2917/19 has the following pins, which are combined with other ...
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NXP Semiconductors WSTOEN=3, WST1=7 Fig 4. Reading from external memory A timing diagram for writing to external memory is shown In between wait-state settings is indicated with arrows. WSTWEN=3, WST2=7 Fig 5. Writing to external memory LPC2917_19_1 Preliminary data sheet ...
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NXP Semiconductors Usage of the idle/turn-around time (IDCY) is demonstrated In are added between a read and a write cycle in the same external memory device. CLK(SYS) CS WE_N / BLS OE_N ADDR DATA WSTOEN=5, WSTWEN=5, WST1=7, WST2=6, IDCY=5 Fig ...
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NXP Semiconductors 8.3 General subsystem 8.3.1 General subsystem clock description The general subsystem is clocked by CLK_SYS_GESS, see 8.3.2 Chip and feature identification 8.3.2.1 Overview The key features are: • Identification of product • Identification of features enabled 8.3.2.2 Description ...
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NXP Semiconductors • Event detection is fully asynchronous clock is required 8.3.4.2 Description The event router allows the event source to be defined, its polarity and activation type to be selected and the interrupt to be masked or ...
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NXP Semiconductors • CLK_SAFE see 8.4.2 Watchdog timer 8.4.2.1 Overview The purpose of the watchdog timer is to reset the ARM9 processor within a reasonable amount of time if the processor enters an error state. The watchdog generates a system ...
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NXP Semiconductors timer has four capture inputs and/or match outputs. Connection to device pins depends on the configuration programmed into the port function-select registers. The two timers located in the MSCSS have no external capture or match pins, but the ...
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NXP Semiconductors Table 14. Timer pins Symbol TIMERx CAP[0] TIMERx CAP[1] TIMERx CAP[2] TIMERx CAP[3] TIMERx MAT[0] TIMERx MAT[1] TIMERx MAT[2] TIMERx MAT[3] 8.4.3.4 Timer clock description The timer modules are clocked by two different clocks; CLK_SYS_PESS and CLK_TMRx (x ...
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NXP Semiconductors 8.4.4.4 UART clock description The UART modules are clocked by two different clocks; CLK_SYS_PESS and CLK_UARTx (x = 0-1), see branch clock for power management. The frequency of all CLK_UARTx clocks is identical since they are derived from ...
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NXP Semiconductors Depending on the operating mode selected, the SPI_CS_OUT outputs operate as an active-HIGH frame synchronization output for Texas Instruments synchronous serial frame format or an active-LOW chip select for SPI. Each data frame is between four and 16 ...
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NXP Semiconductors 8.4.6 General-purpose I/O 8.4.6.1 Overview The LPC2917/19 contains four general-purpose I/O ports located at different peripheral base addresses. In the 144-pin package all four ports are available. All I/O pins are bi-directional, and the direction can be programmed ...
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NXP Semiconductors 8.5 CAN gateway 8.5.1 Overview Controller Area Network (CAN) is the definition of a high-performance communication protocol for serial data communication. The two CAN controllers in the LPC2917/19 provide a full implementation of the CAN protocol according to ...
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NXP Semiconductors • Complete LIN 2.0 message handling and transfer • One interrupt per LIN message • Slave response time-out detection • Programmable sync-break length • Automatic sync-field and sync-break generation • Programmable inter-byte space • Hardware or software parity ...
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NXP Semiconductors control. Several other trigger possibilities are provided for the ADCs (external, cascaded or following a PWM). The capture inputs of both timers can also be used to capture the start pulse of the ADCs. The PWMs can be ...
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NXP Semiconductors Each ADC module has four start inputs. An ADC conversion is started when one of the start ADC conditions is valid: • start 0: ADC external start input pin; can be triggered at a positive or negative edge. ...
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NXP Semiconductors ADC2_EXT_START ADC1_EXT_START pause_0 pause (1) MSCSS TIMER so0 so1 c1 m1 so2 c2 m2 pause_0 c3 m3 MSCSS PAUSE PWM0 TRAP PWM1 TRAP PWM2 TRAP PWM3 TRAP (1) Timers capture in ...
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NXP Semiconductors • CLK_SYS_MSCSS_A clocks the AHB side of the AHB-to-VPB bus bridge • CLK_MSCSS_VPB clocks the subsystem VPB bus • CLK_MSCSS_MTMR0/1 clocks the timers • CLK_MSCSS_PWM0..3 clocks the PWMs. Each ADC has two clock areas; a VPB part clocked ...
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NXP Semiconductors The ADC clock is limited to 4.5 MHz maximum frequency and should always be lower than or equal to the system clock frequency. To meet this constraint or to select the desired lower sampling frequency the clock generation ...
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NXP Semiconductors 8.7.5.4 ADC clock description The ADC modules are clocked from two different sources; CLK_MSCSS_ADCx_VPB and CLK_ADCx ( 2), see and CLK_MSCSS_ADCx_VPB branch clocks for power management ADC is unused both its CLK_MSCSS_ADCx_VPB and ...
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NXP Semiconductors • Automotive dimmer controller: The flexibility of providing waves of a desired duty cycle and cycle period allows the PWM to control the amount of power to be transferred to the load. The PWM functions as a dimmer ...
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NXP Semiconductors 8.7.6.4 Master and slave mode A PWM module can provide synchronization signals to other modules (also called Master mode). The signal sync_out is a pulse of one clock cycle generated when the internal PWM counter (re)starts. The signal ...
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NXP Semiconductors 8.7.7.2 Description See section 8.7.7.3 MSCSS timer-pin description MSCSS timer 0 has no external pins. MSCSS timer 1 has a PAUSE pin available as external pin. The PAUSE pin is combined with other functions on the port pins ...
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NXP Semiconductors AHB2DTL Bridge Fig 11. PCRSS block diagram 8.8.3 PCR subsystem clock description The PCRSS is clocked by a number of different clocks. CLK_SYS_PCRSS clocks the AHB side of the AHB to DTL bus bridge and CLK_PCR_SLOW clocks the ...
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NXP Semiconductors • Generation of 10 and 2 test-base clocks, selectable from several embedded clock sources • Crystal oscillator with power-down • Control PLL with power-down • Very low-power ring oscillator, always on to provide a ’safe clock’ • Seven ...
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NXP Semiconductors LP_OSC Xtal Oscilator Fig 12. Block diagram of the CGU There are two primary clock generators: a low-power ring oscillator (LP_OSC) and a crystal oscillator. See LP_OSC is the source for the BASE_PCR_CLK that clocks the CGU itself ...
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NXP Semiconductors Fig 13. Structure of the clock generation scheme Any output generator (except for BASE_SAFE_CLK and BASE_PCR_CLK) can be connected to either a fractional divider (FDIV0.. one of the outputs of the PLL or to LP_OSC/crystal oscillator ...
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NXP Semiconductors Clock Activity Detection: and values of ’CLK_SEL’ that would select those clocks are masked and not written to the control registers. This is accomplished by adding a clock detector to every clock generator. The RDET register keeps track ...
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NXP Semiconductors Input clock Fig 14. PLL block diagram Triple output phases For applications that require multiple clock phases two additional clock outputs can be enabled by setting register P23EN to ’1’, thus giving three clocks with a 120° phase ...
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NXP Semiconductors 8.8.5 Reset Generation Unit (RGU) 8.8.5.1 Overview The key features of the Reset Generation Unit (RGU) are: • Reset controlled individually per subsystem • Automatic reset stretching and release • Monitor function to trace resets back to source ...
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NXP Semiconductors 8.8.5.3 RGU pin description The RGU module in the LPC2917/19 has the following pins. pins. Table 26. RGU pins Symbol RSTN 8.8.6 Power Management Unit (PMU) 8.8.6.1 Overview This module enables software to actively control the system’s power ...
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NXP Semiconductors Table 27. Branch clock overview Legend: "1" Indicates that the related register bit is tied off to logic HIGH, all writes are ignored "0" Indicates that the related register bit is tied off to logic LOW, all writes ...
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NXP Semiconductors Table 27. Branch clock overview Legend: "1" Indicates that the related register bit is tied off to logic HIGH, all writes are ignored "0" Indicates that the related register bit is tied off to logic LOW, all writes ...
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NXP Semiconductors Interrupt-request masking is performed individually per interrupt target by comparing the priority level assigned to a specific interrupt request with a target-specific priority threshold. The priority levels are defined as follows: • Priority level 0 corresponds to ‘masked’ ...
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NXP Semiconductors Table 28. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter I HIGH-state short-circuit OHS output current. I LOW-state short-circuit OLS output current. General T Storage temperature. stg T Ambient temperature. amb ...
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NXP Semiconductors 11. Static characteristics Table 30. Static characteristics 2 3 DD(CORE) DD(OSC_PLL) DD(IO) measured with respect to ground; positive currents flow into the IC; unless otherwise specified. Symbol Parameter ...
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NXP Semiconductors Table 30. Static characteristics …continued 2 3 DD(CORE) DD(OSC_PLL) DD(IO) measured with respect to ground; positive currents flow into the IC; unless otherwise specified. Symbol Parameter I LOW-state ...
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NXP Semiconductors Table 30. Static characteristics …continued 2 3 DD(CORE) DD(OSC_PLL) DD(IO) measured with respect to ground; positive currents flow into the IC; unless otherwise specified. Symbol Parameter Oscillator R ...
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NXP Semiconductors Table 31. Dynamic characteristics …continued 2 3 DD(CORE) DD(OSC_PLL) DD(IO) respect to ground; positive currents flow into the IC; unless otherwise specified. Symbol Parameter Internal clock f System ...
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NXP Semiconductors Table 31. Dynamic characteristics …continued 2 3 DD(CORE) DD(OSC_PLL) DD(IO) respect to ground; positive currents flow into the IC; unless otherwise specified. Symbol Parameter t Internal write-access a(W)int ...
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NXP Semiconductors 13. Package outline LQFP144: plastic low profile quad flat package; 144 leads; body 1 108 109 pin 1 index 144 DIMENSIONS (mm are the ...
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NXP Semiconductors 14. Soldering 14.1 Introduction There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. ...
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NXP Semiconductors Table 32. SnPb eutectic process (from J-STD-020C) Package thickness (mm) < 2.5 ≥ 2.5 Table 33. Lead-free process (from J-STD-020C) Package thickness (mm) < 1.6 1.6 to 2.5 > 2.5 Moisture sensitivity precautions, as indicated on the packing, ...
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NXP Semiconductors To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward ...
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NXP Semiconductors Table 34. Suitability of IC packages for wave, reflow and dipping soldering methods [1] Mounting Package Surface mount BGA, HTSSON..T LFBGA, SQFP, SSOP..T TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, ...
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NXP Semiconductors 15. Abbreviations Table 35. Abbreviations list Abbreviation AHB BCL BDL CISC DTL SFSP SCL BEL CCO BIST RISC UART VPB LPC2917_19_1 Preliminary data sheet ARM9 microcontroller with CAN and LIN Description Advanced High-performance Bus Buffer Control List Buffer ...
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NXP Semiconductors 16. References [1] UM — LPC2917/19 user manual [2] ARM — ARM web site [3] ARM-SSP — ARM primecell synchronous serial port (PL022) technical reference manual [4] CAN — ISO 11898-1: 2002 road vehicles - Controller Area Network ...
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NXP Semiconductors 17. Revision history Table 36. Revision history Document ID Release date LPC2917_19_1.01 <tbd> • Modifications Part LPC2915 removed • Editorial updates LPC2915_17_19_1 20070917 LPC2917_19_1 Preliminary data sheet ARM9 microcontroller with CAN and LIN Data sheet status Change notice ...
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NXP Semiconductors 18. Legal information 18.1 Data sheet status [1][2] [3] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating ...
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NXP Semiconductors 20. Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 About this document . ...
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NXP Semiconductors 8.7 Modulation and sampling control subsystem . 31 8.7.1 Overview ...