ZLF645 MAXIM [Maxim Integrated Products], ZLF645 Datasheet - Page 86

• Manufacturer Part Number: ZLF645
• Description: Flash MCUs with Learning Amplification
• Manufacturer: MAXIM [Maxim Integrated Products]

Table 35. Flash Page Select Register (FPS)
19-4572; Rev 0; 4/09
Bit Position
[7]
[6:0]
Bits
Field
Reset
R/W
Address
Flash Sector Protect Register
IFEN
R/W
7
0
page erase command must be initiated by the ICP. Information Block page erase or pro-
gramming operations initiated by the CPU are ignored by the Flash Controller. In the case
of an Information Block programming or page erase operation initiated by the ICP, the
FPS register must first be programmed with
Block or else the operation will be ignored by the Flash Controller. For Information Block
programming through the ICP, bits 12 through 6 of the address must equal 
bits 6 through 0 of the FPS register for the Flash Controller to execute the operation.
The Flash Sector Protect (FSEC) register (see
Page Select (FPS) register. It is accessed by first writing
register with the Flash Controller in ‘locked’ state, and then writing to the register file
address location given for the Flash Page Select (FPS) register.
The FSEC register selects which of the eight available Flash memory sectors is to be pro-
tected from CPU initiated programming or page erase operations. For ICP initiated pro-
gramming or page erase operations, the settings within the FSEC register are ignored by
the Flash Controller. The reset state of each Sector Protect bit in the FSEC register is its
unprotected state or 0 value. After a sector is protected by setting its corresponding regis-
ter bit to 1, it cannot be unprotected (the register bit cannot be cleared) without powering
down the device.
Value
0
1
0
1
R/W
6
0
Description
IFEN —Information Area Enable
Operation to be performed on Flash main memory.
Operation to be performed on Flash Information Area.
PAGE —Page Select
This 7-bit field identifies the Flash main memory page for Page Erase and
Page unlocking. Program Memory Address[15:9] = PAGE[6:0]. 
The least significant 2 bits of Page identifies the Flash Information page for
Page Erase and Page unlocking. The upper significant bits must be logic 0’s.
R/W
5
0
Bank F, Register address: 02H
R/W
4
0
PAGE
R/W
83H
Table
3
0
to point to page 3 of the Information
36) address is shared with the Flash
5EH
R/W
ZLF645 Series Flash MCUs
2
0
Flash Control Register Definitions
to the Flash Control (FCTL)
Product Specification
R/W
1
0
R/W
0
0
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