COP8ACC720M9-RE NSC [National Semiconductor], COP8ACC720M9-RE Datasheet - Page 12

• Manufacturer Part Number: COP8ACC720M9-RE
• Description: 8-Bit CMOS OTP Microcontroller with 16k Memory and High Resolution A/D
• Manufacturer: NSC [National Semiconductor]

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Functional Description
will fail Blank Check and will fail Verify operations. A Read
operation will fill the programmer’s memory with 00(hex).
The Security Byte itself is always readable with value of
00(hex) if unsecure and FF(hex) if secure.
DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data and
Pin), the control registers, the MICROWIRE/PLUS SIO shift
register, and the various registers, and counters associated
with the timers (with the exception of the IDLE timer). Data
memory is addressed directly by the instruction or indirectly
by the B, X, and SP pointers.
The data memory consists of 128 bytes of RAM. Sixteen
bytes of RAM are mapped as “registers” at addresses 0F0 to
0FF Hex. These registers can be loaded immediately, and
also decremented and tested with the DRSZ (decrement
register and skip if zero) instruction. The memory pointer
registers X, B and SP are memory mapped into this space at
address locations 0FC to 0FF Hex respectively, with the
other registers being available for general usage.
The instruction set permits any bit in memory to be set, reset
or tested. All I/O and registers (except A and PC) are
memory mapped; therefore, I/O bits and register bits can be
directly and individually set, reset and tested. The accumula-
tor (A) bits can also be directly and individually tested.
Note: RAM contents are undefined upon power-up.
Reset
The RESET input when pulled low initializes the microcon-
troller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the data and configuration
registers for ports L and G are cleared, resulting in these
Ports being initialized to the TRI-STATE mode. Pin G1 of the
G Port is an exception (as noted below) since pin G1 is dedi-
cated as the WATCHDOG and/or Clock Monitor error output
pin. Port D is set high. The PC, PSW, ICNTRL and
CNTRL-control registers are cleared. The Comparator Se-
lect Register is cleared. The S register is initialized to zero.
The Multi-Input Wakeup registers WKEN and WKEDG are
cleared. Wakeup register WKPND is unknown. The stack
pointer, SP, is initialized to 6F Hex.
The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, with the
WATCHDOG service window bits set and the Clock Monitor
bit set. The WATCHDOG and Clock Monitor circuits are in-
hibited during reset. The WATCHDOG service window bits
being initialized high default to the maximum WATCHDOG
service window of 64k t
being initialized high will cause a Clock Monitor error follow-
ing reset if the clock has not reached the minimum specified
frequency at the termination of reset. A Clock Monitor error
will cause an active low error output on pin G1. This error
output will continue until 16 t
the clock frequency reaching the minimum specified value,
at which time the G1 output will enter the TRI-STATE mode.
The external RC network shown in Figure 6 should be used
to ensure that the RESET pin is held low until the power sup-
ply to the chip stabilizes.
WARNING:
When the device is held in reset for a long time it will con-
sume high current (typically about 7 mA). This is not true for
the equivalent ROM device (COP8ACC5).
C
clock cycles. The Clock Monitor bit
C
-32 t
C
clock cycles following
(Continued)
12
Oscillator Circuits
The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7 (crystal configuration). The CKI input fre-
quency is divided down by 10 to produce the instruction
cycle clock (t
RC
Figure 7 shows the Crystal and R/C Oscillator diagrams.
CRYSTAL OSCILLATOR
CKI and CKO can be connected to make a closed loop crys-
tal (or resonator) controlled oscillator.
Table 1 shows the component values required for various
standard crystal values.
R/C OSCILLATOR
By selecting CKI as a single pin oscillator input, a single pin
R/C oscillator circuit can be connected to it. CKO is available
as a general purpose input, and/or HALT restart input.
Note: Use of the R/C oscillator option will result in higher electromagnetic
Table 2 shows the variation in the oscillator frequencies as
functions of the component (R and C) values.
Note 18: 3k
Note 19: 50 pF
(k )
(k )
TABLE 1. Crystal Oscillator Configuration, T
R1
3.3
5.6
6.8
R
0
0
0
>
TABLE 2. RC Oscillator Configuration, T
5 x POWER SUPPLY RISE TIME
emissions.
FIGURE 6. Recommended Reset Circuit
(M )
(pF)
100
100
R2
82
C
1
1
1
R
C
).
C
200k
(pF)
200
CKI Freq
2.2 to 2.7
1.1 to 1.3
0.9 to 1.1
C1
30
30
200 pF
(MHz)
100–150
30–36
30–36
(pF)
C2
Instr. Cycle
8.8 to 10.8
3.7 to 4.6
7.4 to 9.0
CKI Freq
(µs)
(MHz)
0.455
10
4
DS012869-6
A
Conditions
Conditions
V
V
V
V
V
V
= 25˚C
A
CC
CC
CC
CC
CC
CC
= 25˚C
= 5V
= 5V
= 5V
= 5V
= 5V
= 5V