M30240ECFP MITSUBISHI [Mitsubishi Electric Semiconductor], M30240ECFP Datasheet
M30240ECFP
Related parts for M30240ECFP
M30240ECFP Summary of contents
Page 1
PRELIMINARY MITSUBISHI ELECTRONICS AMERICA, INC. M30240 M30240 Group Specification Description 1-3 Features...............................................................1-3 Applications......................................................... ...
Page 2
MITSUBISHI ELECTRONICS AMERICA, INC. 1-2 ...
Page 3
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Features 1.0 Description The M30240 group is a 16-bit microcomputer based on the M16C family core technology. They are single-chip USB peripheral microcontrollers based on the ...
Page 4
Specifications in this manual are tentative and subject to change Pin Configuration 1.3 Pin Configuration Figure 1.1 shows the pin configuration (top view P03/KI3 65 P02/KI2 66 P01/KI1 67 P00/KI0 ...
Page 5
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Block Diagram 1.4 Block Diagram Figure 1 block diagram of the M30240 group I/O ports Port P0 Port P1 Internal peripheral functions ...
Page 6
Specifications in this manual are tentative and subject to change Performance outline 1.5 Performance outline Table 1 performance outline of the M30240 group. Table 1.1: Performance outline of M30240 group Item Number of basic instructions Shortest instruction execution ...
Page 7
... Table 1.2 shows the Package Number, type, ROM and RAM Capacity for M30240 Group. Table 1.2: M30240 Group Type ROM Capacity M30240M5 40K bytes M30240M6 48K bytes M30240ECFP 128K bytes SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Package type Package 80P6N ROM No. Omitted for blank one-time PROM version,and EPROM version ...
Page 8
Specifications in this manual are tentative and subject to change Pin Description 1.6 Pin Description Table 1.3: Figure Pin Description Pin # Name /(NMI ...
Page 9
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Pin Description Table 1.3: Figure Pin Description Pin # Name I / ...
Page 10
Specifications in this manual are tentative and subject to change Overview 1.7 Overview The M30240 group is a single chip PC peripheral microcontroller based on the Universal Serial Bus (USB) Version 1.1 specification. This device provides interface between a USB- ...
Page 11
Specifications in this manual are tentative and subject to change Central Processing Unit (CPU) 2.0 Operation of Functional Blocks The M30240 group accommodates certain units in a single chip. These units include ROM and RAM to store instructions and data, ...
Page 12
Specifications in this manual are tentative and subject to change Central Processing Unit (CPU) Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H), and low-order bits as (R0L/R1L). In some instructions, registers ...
Page 13
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Central Processing Unit (CPU) 2.1.8.7 Bit 6: Interrupt enable flag (I flag) This flag enables a maskable interrupt. An interrupt is disabled when this flag is ...
Page 14
Specifications in this manual are tentative and subject to change Processor Mode 2.2 Processor Mode Figure 1.7 shows the processor mode registers 0 and 1. Processor mode register 0 (Note Symbol ...
Page 15
... See Section 2.12 on interrupts for further details. Addresses below xxxxx are RAM. For example, in M30240ECFP, 5K bytes of internal RAM are 16 mapped to the space from 00400 used when calling subroutines and when interrupts are generated.The SFR area is mapped to 00000 to 003FF ...
Page 16
Specifications in this manual are tentative and subject to change SFR MAP 2.4 SFR MAP The table below shows the peripheral control registers, their addresses, names, acronyms, and values after reset. Address 0000 16 0001 16 0002 16 0003 16 ...
Page 17
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change SFR MAP Address 0040 16 0041 16 0042 16 0043 16 Suspend interrupt control register 0044 16 0045 16 0046 Resume interrupt control register 16 0047 ...
Page 18
Specifications in this manual are tentative and subject to change SFR MAP Address USB reserved 0320 16 0321 USB control/status register 16 USB EP 2 OUT control/status register 0322 16 0323 USB max packet ...
Page 19
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change SFR MAP Address 0370 16 0371 16 0372 16 0373 16 0374 16 0375 16 0376 16 0377 Reserved 16 0378 UART2 transmit / receive mode ...
Page 20
Specifications in this manual are tentative and subject to change SFR MAP Address UART transmit / receive control register 2 03B0 16 03B1 16 03B2 16 03B3 16 03B4 16 03B5 16 03B6 16 03B7 16 03B8 DMA0 cause select ...
Page 21
Specifications in this manual are tentative and subject to change SFR MAP Address Port P8 03F0 16 03F1 16 03F2 Port P8 direction register 16 03F3 16 03F4 Port P10 16 03F5 16 03F6 Port P10 direction register 16 03F7 ...
Page 22
Specifications in this manual are tentative and subject to change Reset 2.5 Reset There are two types of resets: hardware and software. In both cases, operation is the same after the reset. (See “Software Reset” for further details regarding software ...
Page 23
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Software Reset When the RESET pin level = “L”, all ports change to input mode (floating.) Table 1.4 shows the status of the other pins while ...
Page 24
Specifications in this manual are tentative and subject to change Clock Control 2.8 Clock Control Figure 1.12 shows the block diagram of the clock-generating circuit. CM10 “1” Write signal RESET Software reset NMI Interrupt request level judgment output WAIT instruction ...
Page 25
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Clock Control 2.8.3 Peripheral function clock 2.8.3.1 • f1, f8, f32 The clock for the peripheral devices is derived from the main clock or by dividing ...
Page 26
Specifications in this manual are tentative and subject to change Stop Mode 2.9 Stop Mode Writing “1” to the all-clock stop control bit (bit 0 at address 0007 microcomputer enters stop mode. In stop mode, the content of the internal ...
Page 27
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Power Control 2.11.2 Division by 4 mode The main clock is divided obtain the internal clock . 2.11.3 Division by 8 mode The ...
Page 28
Specifications in this manual are tentative and subject to change Protection 2.13 Protection The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. Figure 1.14 ...
Page 29
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Interrupts 2.14 Interrupts Table 1.8 and Table 1.9 show the interrupt sources and vector table addresses. When an interrupt is received, the program is executed from ...
Page 30
Specifications in this manual are tentative and subject to change Interrupts Table 1.9: Interrupt vectors (variable interrupt vector addresses) Vector table addresses Software interrupt number Address(L) to Address(H) Software interrupt number (Note 1) Software interrupt number ...
Page 31
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Interrupts 2.14.1 Interrupt control registers Peripheral I/O interrupts have their own interrupt control registers. Table 1.10 shows the addresses of the interrupt control registers. Figure 1.16 ...
Page 32
Specifications in this manual are tentative and subject to change Interrupts Interrupt control register Bit symbol Nothing is assigned. These bits can neither be set nor reset. When read, their contents are ...
Page 33
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Interrupts 2.14.2 Interrupt priority The order of priority when two or more interrupts are generated simultaneously is determined by both hardware and software. The interrupt priority ...
Page 34
Specifications in this manual are tentative and subject to change Interrupts Priority level of each interrupt INT1 USB Reset Timer B0 Timer A3 Timer A1 USB Resume USB Suspend USB Function INT0 Timer B1 Timer A4 Timer A2 USB SOF ...
Page 35
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change NMI Interrupt 2.14.3 Flag changes When an interrupt request is received, the stack pointer select flag (U flag) changes to “0” and the flag register (FLG) ...
Page 36
Specifications in this manual are tentative and subject to change Key-Input Interrupt 2.14 Key-Input Interrupt If the direction register of any of pin of Port0 or Port1 is set for input and a falling edge is input to that port, ...
Page 37
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Key-Input Interrupt 2.14.4 Registers related to the key-input interrupt Figure 1.19 shows the memory map of key-input interrupt-related registers Figure 1.19: Memory Map of key input ...
Page 38
Specifications in this manual are tentative and subject to change Address Match Interrupt 2.15 Address Match Interrupt An address match interrupt is generated when the address match interrupt address register contents match the program counter value. Two address match interrupts ...
Page 39
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Watchdog Timer 2.16 Watchdog Timer The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is 39a 15-bit ...
Page 40
Specifications in this manual are tentative and subject to change Watchdog Timer Internal clock Write to the watchdog timer start register (address 000E ) 16 RESET Figure 1.21: Block diagram of watchdog timer Watchdog timer control register ...
Page 41
Specifications in this manual are tentative and subject to change Frequency Synthesizer Circuit 2.17 Frequency Synthesizer Circuit The Frequency Synthesizer Circuit generates a 48MHz clock needed by the USB block and a clock f that are both a multiple of ...
Page 42
Specifications in this manual are tentative and subject to change Frequency Synthesizer Circuit 2.17.2 Multiplier Clock multiplied up version of clock f VCO and the clock input to the multiplier (f • ...
Page 43
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Frequency Synthesizer Circuit The FSC0 bit in the FSC Control Register enables the frequency synthesizer block. When disabled (FSC0 = “0”), f is held at either ...
Page 44
Specifications in this manual are tentative and subject to change Universal Serial Bus 2.18 Universal Serial Bus The Universal Serial Bus (USB) has the following features: • Complete USB Specification (version 1.1) Compatibility • Error-handling capabilities • FIFOs: • Endpoint ...
Page 45
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Universal Serial Bus 2.18.1.2 Generic Function Interface The GFI handles all USB standard requests from the host through the control endpoint (endpoint zero), han- dles Bulk, ...
Page 46
Specifications in this manual are tentative and subject to change Universal Serial Bus 2.18.2.1 USB Function Interrupt The USB Function Interrupt can be triggered by 10 sources; many of these may be cause by several different events. Interrupt status flags ...
Page 47
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Universal Serial Bus 2.18.2.4 USB SOF Interrupt The USB SOF (Start-Of-Frame) Interrupt is used to control the transfer of isochronous data. The USB FCU generates a ...
Page 48
Specifications in this manual are tentative and subject to change Universal Serial Bus The status of endpoint 1-4 IN FIFOs for both of the above cases can be obtained from the IN CSR of the cor- responding IN FIFO as ...
Page 49
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Universal Serial Bus 2.18.3.3 Interrupt Endpoints: Any endpoint can be used for interrupt transfers. For normal interrupt transfers, the interrupt transactions be- have the same as ...
Page 50
Specifications in this manual are tentative and subject to change Universal Serial Bus 2.18.4.2 USB Control Register The USB Control Register, shown in Figure 1.31, is used to control the USB FCU. This register is not reset by a USB ...
Page 51
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Universal Serial Bus 2.18.4.4 The USB Power Management Register The USB Power Management Register, shown in Figure 1.33, is used for power management in the USB ...
Page 52
Specifications in this manual are tentative and subject to change Universal Serial Bus 2.18.4.5 USB Interrupt Status Registers 1 and 2 USB Interrupt Status Registers 1 and 2, shown in Figure 1.34 and Figure 1.35, are used to indicate the ...
Page 53
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Universal Serial Bus USB Interrupt Status Register Bit symbol INTST8 INTST9 Reserved Reserved INTST12 INTST13 ...
Page 54
Specifications in this manual are tentative and subject to change Universal Serial Bus USB Interrupt Enable Register Bit symbol Reserved Figure 1.36: USB Interrupt Enable Register 1 USB Interrupt Enable ...
Page 55
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Universal Serial Bus 2.18.4.8 USB Frame Number Registers The USB Frame Number Low Register, shown in Figure 1.38, contains the lower 8 bits of the 11-bit ...
Page 56
Specifications in this manual are tentative and subject to change Universal Serial Bus 2.18.4.10 USB DMAx Request Registers The USB DMAx Request Registers, shown in Figure 1.41 and Figure 1.42, are used to select which USB End- point x FIFO ...
Page 57
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Universal Serial Bus 2.18.4.12 Endpoint 0 CSR (Control and Status Register) The Endpoint 0 CSR (Control and Status Register), shown in Figure 1.44 contains the control ...
Page 58
Specifications in this manual are tentative and subject to change Universal Serial Bus data will be in the FIFO. For this case, because the SETUP_END bit is set near the beginning of the packet when the SETUP PID is encountered ...
Page 59
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Universal Serial Bus 2.18.4.14 USB Endpoint 0 OUT WRT CNT Register The USB Endpoint 0 OUT WRT CNT Register, shown in Figure 1.46, contains the number ...
Page 60
Specifications in this manual are tentative and subject to change Universal Serial Bus The CPU writes a “1” to this bit to flush the IN FIFO. When there is one packet in the IN FIFO, a flush causes the IN ...
Page 61
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Universal Serial Bus When endpoint is required to initialize the data toggle sequence bit (i.e. reset to DATA0 for the next data pack- et), the CPU ...
Page 62
Specifications in this manual are tentative and subject to change Universal Serial Bus 2.18.4.18 USB Endpoint x OUT MAXP Register The USB Endpoint x OUT MAXP Register, shown in Figure 1.50, indicates the maximum packet size (MAXP Endpoint ...
Page 63
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change DMAC 2.19 DMAC This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to memory without using the CPU.Table 1.14 ...
Page 64
Specifications in this manual are tentative and subject to change DMAC DMA0 transfer counter reload register TCR0 (16) DMA0 transfer counter TCR0 (16) DMA1 transfer counter reload register TCR1 (16) DMA1 transfer counter TCR1 (16) Note: Pointer is incremented by ...
Page 65
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change DMAC DMAi control register Bit symbol DMBIT DMASL DMAS DMAE DSD DAD Nothing is assigned. These bits can ...
Page 66
Specifications in this manual are tentative and subject to change DMAC 2.19.1 Transfer cycle The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area (source read) and the bus cycle ...
Page 67
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change DMAC (1) 8-bit transfers 16-bit transfers from even address and the source address is even. CLKout Address CPU use bus Data CPU use bus (2) 16-bit ...
Page 68
Specifications in this manual are tentative and subject to change Timers 2.20 Timers There are eight 16-bit timers. These timers can be classified by function into timers A (five) and timers B (three). All these timers function independently. Figure 1.58 ...
Page 69
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Timer A 2.21 Timer A Figure 1.59, Figure 1.60,Figure 1.61, and Figure 1.62 show the timer A-related registers. Except in event counter mode, timers A0 through ...
Page 70
Specifications in this manual are tentative and subject to change Timer A Timer Ai register (Note) (b15) (b8 Count start flag Up/down flag ...
Page 71
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Timer A One-shot start flag Bit symbol TA0OS TA1OS TA2OS TA3OS TA4OS Nothing is assigned. This bit can ...
Page 72
Specifications in this manual are tentative and subject to change Timer A 2.21.1 Timer mode In this mode, the timer counts an internally generated count source. See Table 1.17 below. Figure 1.63 shows the timer Ai mode register in timer ...
Page 73
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Timer A 2.21.2 Event counter mode In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can count ...
Page 74
Specifications in this manual are tentative and subject to change Timer A Timer Ai mode register Bit symbol TMOD0 TMOD1 Note 1: In event counter mode, the count source ...
Page 75
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Timer A Table 1.19: Timer specification in even counter mode (when processing two-phase pulse signal with timers A2, A3, and A4) Item Count Source •Two-phase pulse ...
Page 76
Specifications in this manual are tentative and subject to change Timer A Timer Ai mode register (When not using two-phase pulse signal processing) Symbol TAiMR 0398 0 0 ...
Page 77
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Timer A 2.21.3 One-shot timer mode In this mode, the timer operates only once (See Table 1.20 ). When a trigger occurs, the timer starts up ...
Page 78
Specifications in this manual are tentative and subject to change Timer A 2.21.4 Pulse-width modulation (PWM) mode In this mode, the timer outputs pulses of a given width in succession (See Table 1. this mode, the counter functions ...
Page 79
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Timer A Condition : Reload register = 0003 (rising edge of TA Count source “H” TA pin iIN input signal “L” “H” PWM pulse output from ...
Page 80
Specifications in this manual are tentative and subject to change Timer B 2.22 Timer B Figure 1.70 shows the block diagram of timer B. Figure 1.71 and Figure 1.72 show the timer B-related registers. Use the timer Bi mode register ...
Page 81
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Timer B Timer Bi register (Note) (b15) b7 Count start flag Figure 1.72: Timer B-related registers 2.22.1 Timer mode In ...
Page 82
Specifications in this manual are tentative and subject to change Timer B Timer Bi mode register Note 1: Timer B0. Note 2: Timer B1, Timer B2. Figure 1.73: Timer Bi ...
Page 83
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change UART0 through UART2 2.23 UART0 through UART2 Serial I/O is configured as three channels: UART0, UART1, and UART2. UART0, UART1, and UART2 each have an exclusive ...
Page 84
Specifications in this manual are tentative and subject to change UART0 through UART2 Figure 1.75 and Figure 1.76 show the block diagram of the transmit/receive unit. 1SP SP SP RxDi 2SP 0 0 2SP SP SP PAR 1SP Figure 1.75: ...
Page 85
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change UART0 through UART2 UARTi ( has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/O mode ...
Page 86
Specifications in this manual are tentative and subject to change UART0 through UART2 UARTi transmit buffer register (b15) (b8 UARTi receive buffer register (b8) (b15 UARTi bit rate generator b7 b0 Figure 1.77: Serial ...
Page 87
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change UART0 through UART2 UARTi transmit/receive mode register Bit symbol SMD0 Serial I/O mode select bit SMD1 SMD2 CKDIR ...
Page 88
Specifications in this manual are tentative and subject to change UART0 through UART2 UARTi transmit/receive control register symbol CLK0 CLK1 CRS TXEPT CRD Nothing is assigned. This bit can neither be ...
Page 89
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change UART0 through UART2 UARTi transmit/receive control register Symbol UiC1(i=0,1) Bit symbol Nothing is ...
Page 90
Specifications in this manual are tentative and subject to change UART0 through UART2 UART transmit/receive control register Bit symbol U0IRS U1IRS U0RRM U1RRM CLKMD0 CLKMD1 Reserved Nothing is assigned. This bit ...
Page 91
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change UART0 through UART2 2.23.1 Clock synchronous serial I/O mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 1.24 ...
Page 92
Specifications in this manual are tentative and subject to change UART0 through UART2 Table 1.25: Specifications of clock synchronous serial I/O mode (2) Item • CLK polarity selection Whether transmit data is output/input at the rising edge or falling edge ...
Page 93
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change UART0 through UART2 Table 1.26 lists the functions of the input/output pins during clock synchronous serial I/O mode. This table shows the pin functions when the ...
Page 94
Specifications in this manual are tentative and subject to change UART0 through UART2 Transfer clock “1” Transmit enable “0” bit (TE) “1” Transmit buffer empty flag (Tl) “0” “H” CTSi “L” CLKi TxDi Transmit “1” register empty “0” flag (TXEPT) ...
Page 95
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change UART0 through UART2 2.23.1.1 Polarity select function As shown in Figure 1.84, the CLK polarity select bit (bit 6 at addresses 03A4 lection of the polarity ...
Page 96
Specifications in this manual are tentative and subject to change UART0 through UART2 2.23.1.3 Transfer clock output from multiple pins function (UART1) This function allows the setting two transfer clock output pins and choosing one of the two to output ...
Page 97
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change UART0 through UART2 2.23.2 Clock asynchronous serial I/O (UART) mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer ...
Page 98
Specifications in this manual are tentative and subject to change UART0 through UART2 Table 1.28: Specifications of UART Mode (2) Item • Sleep mode selection (UART0, UART1) This mode is used to transfer data to and from one of multiple ...
Page 99
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change UART0 through UART2 Table 1.29 lists the functions of the input/output pins during UART mode. Note that for a period from when the UARTi operation mode ...
Page 100
Specifications in this manual are tentative and subject to change UART0 through UART2 • Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) Transfer clock “1” Transmit enable bit(TE) “0” Data is set ...
Page 101
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change UART0 through UART2 Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) BRGi count source “1” Receive enable bit ...
Page 102
Specifications in this manual are tentative and subject to change UART0 through UART2 2.23.2.3 TxD, RxD I/O polarity reverse function (UART2) This function is to reverse TxD pin output and RxD pin input. The level of any data to be ...
Page 103
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change UART0 through UART2 2.23.3 Clock-asynchronous serial I/O mode (compliant with the SIM interface) The SIM interface is used for connecting the microcomputer with a memory card ...
Page 104
Specifications in this manual are tentative and subject to change UART0 through UART2 Transfer clock “1” Transmit enable bit(TE) “0” Data is set in UARTi transmit buffer register “1” Transmit buffer empty flag(TI) “0” Start bit TxD ...
Page 105
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change UART0 through UART2 2.23.3.1 Function for outputting a parity error signal With the error signal output enable bit (bit 7 of address 037D the TxD2 pin ...
Page 106
Specifications in this manual are tentative and subject to change A-D Converter 2.24 A-D Converter The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling amplifier. Pins P100 to P107 function as the analog ...
Page 107
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change A-D Converter f AD 1/2 V REF VCUT=0 Resistor ladder AV SS VCUT=1 Successive conversion register Addresses (03C1 , 03C0 ) A-D register 0(16 ...
Page 108
Specifications in this manual are tentative and subject to change A-D Converter A-D control register 0 (Note Note 1: If the A-D control register is rewritten during A-D conversion, the conversion ...
Page 109
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change A-D Converter A-D control register 2 (Note Bit symbol Reserved bit Nothing is assigned. These ...
Page 110
Specifications in this manual are tentative and subject to change A-D Converter 2.24.1 One-shot mode In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D con- version.Table 1.32 shows the specifications of ...
Page 111
Specifications in this manual are tentative and subject to change A-D Converter 2.24.2 Repeat mode In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conver- sion. Table 1.33 shows the specifications ...
Page 112
Specifications in this manual are tentative and subject to change A-D Converter 2.24.3 Single sweep mode In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D conversion. Table 1.34 shows the ...
Page 113
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change A-D Converter 2.24.4 Repeat sweep mode 0 In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat ...
Page 114
Specifications in this manual are tentative and subject to change A-D Converter 2.24.5 Repeat sweep mode 1 In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins select- ed using the ...
Page 115
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change A-D Converter 2.24.6 Sample and hold Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D4 sample and hold ...
Page 116
Specifications in this manual are tentative and subject to change CRC Calculation Circuit 2.25 CRC Calculation Circuit The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The microcomputer uses a generator polynomial of CRC_CCITT (X16 + ...
Page 117
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Programmable I/O Ports 2.26 Programmable I/O Ports There are 63 programmable I/O ports P3 (excluding P85), and P10. Each port can ...
Page 118
Specifications in this manual are tentative and subject to change Programmable I/O Ports Data bus P70, P72, P74, P76, Data bus P80 ...
Page 119
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Programmable I/O Ports P10 to P10 ...
Page 120
Specifications in this manual are tentative and subject to change Programmable I/O Ports BYTE BYTE Input CNVss CNVss Input RESET RESET Input Note: Do not apply a voltage higher than Vcc to each port Figure 1.109: Programmable I/O Ports (3) ...
Page 121
Specifications in this manual are tentative and subject to change Programmable I/O Ports Port Pi register Port P8 register Figure 1.111: Port register Pull-up ...
Page 122
Specifications in this manual are tentative and subject to change Programmable I/O Ports Port 2 Drive Capacity Register Bit symbol P2DR0 P2DR1 P2DR2 P2DR3 P2DR4 P2DR5 P2DR6 P2DR7 Timer A Output drive ...
Page 123
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Programmable I/O Ports Figure 1.114: Example connection unused pins Table 1.37: Example connection of unused pins in single-chip mode Pin name Ports P0 to P3, P6 ...
Page 124
Specifications in this manual are tentative and subject to change Usage Precautions 3.0 Usage 3.1 Usage Precautions 3.1.1 A-D Converter • Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register ...
Page 125
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Usage Precautions 3.1.4 DMAC When the DMA enable bit (bit 3 of DM0CON and DM1CON) is set to “1”, the DMAC active state. ...
Page 126
Specifications in this manual are tentative and subject to change Usage Precautions 3.1.8 Timer A (timer mode) • Reading the Timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading ...
Page 127
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Usage Precautions Note: Never expose to 150˚C exceeding 100 hours. Figure 1.115: Programming and test flow for One-time PROM (OTP) version SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programming ...
Page 128
Specifications in this manual are tentative and subject to change Electrical 4.0 Specifications 4.1 Electrical Table 1.38: Absolute maximum ratings only, not operating conditions Symbol Parameter V Supply voltage CC AV Analog supply voltage CC Port0, Port1, Port2, Port3, Port6, ...
Page 129
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Electrical Table 1.40: Electrical characteristics (Vcc=4.1~5.25V, Vss=0V, Ta f(Xin) = 12MHz Symbol Parameter Port0, Port1, Port2, Port3, Port6, V High output voltage ...
Page 130
Specifications in this manual are tentative and subject to change Timing Table 1.41: USB Electrical Characteristics (Vcc=4.1~5.25V, Vss=0V, Ta= 0 Symbol Parameter V D+, D- I=18.3 mA, RX=33 , VXcap =3 D+, D- I=18.3 mA, RX=33 , ...
Page 131
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Timing Table 1.44: Timer A input (counter input in event counter mode) Symbol tc( ) TAi input cycle time TA IN tw( ) TAi input HIGH ...
Page 132
Specifications in this manual are tentative and subject to change Timing Table 1.50: Serial I/O Symbol tc( ) CLKi input cycle time CK tw( ) CLKi input HIGH pulse width CKH tw( ) CLKi input LOW pulse width CKL td( ...
Page 133
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Timing Diagrams- Peripheral/interrupt 4.3 Timing Diagrams- Peripheral/interrupt TAi input IN TAi input OUT TAi input OUT (Up/down input) During event counter mode TAi input IN (When ...
Page 134
Specifications in this manual are tentative and subject to change Frequency Synthesizer Interface and DC-DC Converter 5.0 Applications 5.1 Frequency Synthesizer Interface and DC-DC Converter This section presents the recommended method of setting up and using the frequency synthesizer that ...
Page 135
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Frequency Synthesizer Interface and DC-DC Converter 5.1.2 Set up of Frequency Synthesizer and DC-DC Converter Frequency f(Xin) Synthesizer enable FSE USBCLK (48MHz) Figure 1.118: PLL, DC-DC ...
Page 136
Specifications in this manual are tentative and subject to change Frequency Synthesizer Interface and DC-DC Converter • Enable the USB clock by setting USBC5 (bit 5 of USBC “1”. (If the USB clock and FCU are enabled before ...
Page 137
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Frequency Synthesizer Interface and DC-DC Converter 5.1.2.3 Set up after USB Suspend Detected A USB Suspend occurs if the USB FCU does not detect any bus ...
Page 138
Specifications in this manual are tentative and subject to change Attach/Detach Function 5.1.2.5 PLL Lock Bit The PLL lock bit is used to indicate when the PLL is first locked. Accordingly, after the PLL is enabled and it has been ...
Page 139
Preliminary Specifications REV. E Specifications in this manual are tentative and subject to change Low Pass Filter Network 5.3 Low Pass Filter Network All passive components should be in close proximity to pin 78 (LPF), capacitors should be X7R di- ...
Page 140
Specifications in this manual are tentative and subject to change USB Transceiver 5.4 USB Transceiver When using the on-chip voltage converter to supply the necessary 3.3V to the driver circuit, a capac- itor network must be connected between Ext. Cap ...
Page 141
Specifications in this manual are tentative and subject to change Programming Notes 5.5 Programming Notes 5.5.1 Accessing USB IN/OUT CSR Registers Do not use read-modify-write instruction on these registers because they contain control and status bits that can be changed ...
Page 142
Specifications in this manual are tentative and subject to change Programming Notes Below is an example of how to set/reset the ISO bit of the IN CSR register (for initializing the respective endpoint as an isochronous endpoint): [R1L] = [EPiICS].B ...