TMS470R1B512 AD [Analog Devices], TMS470R1B512 Datasheet

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... All other trademarks are the property of their respective owners. ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 External Clock Prescale (ECP) Module – ...

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... HET[3] 138 HET[4] 139 HET[5] 140 HET[6] 141 HET[7] 142 GIOC[1] 143 GIOC[2] 144 A. GIOA[0]/INT0 (pin 39 input-only GIO pin. 2 TMS470R1B512 144-Pin PGE Package (Top View) Submit Documentation Feedback www.ti.com 72 AWD 71 HET[18] 70 HET[19] 69 HET[20] 68 HET[21] 67 HET[22] 66 SPI2SCS 65 SPI2ENA ...

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... TMS470R1x Direct Memory Access (DMA) Controller Reference Guide (literature number SPNU194). The B512 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-word, and word modes. (1) The TMS470R1B512 device name will be referred to as either the full device name or as B512 throughout the remainder of this document. 16/32-Bit RISC Flash Microcontroller SPNS107A – ...

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... TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented with a 32-bit-wide data bus interface. The flash operates with a system clock frequency MHz. When in pipeline mode, the flash operates with a system clock frequency MHz ...

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... The B512 device has both the logic and registers for a full 16-channel FIFO MibADC implemented and all 16 pins are available externally. 1.81 – 2.05 V 3.0 – 3.6 V 144 PGE Submit Documentation Feedback TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 Table 1 identifies all the COMMENTS Table 3, Memory Selection Assignment). ...

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... TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 External Pins V CCP FLASH (512K Bytes) FLTP1 14 Sectors FLTP2 TRST TCK TDI TDO TMS TMS2 TMS470R1x System Module RST AWD TEST PORRST DMA Controller 16 Channels CLKOUT ECP A. GIOA[0]/INT0 is an input-only pin. ...

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... IPU (20 A) HECC1 transmit pin or GIO pin HECC1 receive pin or GIO pin HIGH-END CAN CONTROLLER 2 (HECC2) IPU (20 A) HECC2 transmit pin or GIO pin HECC2 receive pin or GIO pin Submit Documentation Feedback TMS470R1B512 SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 DESCRIPTION 7 ...

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... TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 TERMINAL (1) (2) TYPE NAME NO. GIOA[0]/INT0 39 3.3-V I GIOA[1]/INT1/ 40 ECLK GIOA[2]/INT2 41 GIOA[3]/INT3 42 GIOA[4]/INT4 36 GIOA[5]/INT5 35 GIOA[6]/INT6 34 GIOA[7]/INT7 33 GIOB[0] 46 GIOB[1] 58 GIOB[2] 59 GIOB[3] 60 GIOB[4] 61 GIOB[ ...

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... SCI2 clock. SCI2CLK can be programmed as a GIO pin. IPU (20 A) SCI2 data receive. SCI2RX can be programmed as a GIO pin. IPU (20 A) SCI2 data transmit. SCI2TX can be programmed as a GIO pin. Submit Documentation Feedback TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 DESCRIPTION 9 ...

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... TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 TERMINAL (1) (2) TYPE NAME NO. CLKOUT 83 3.3-V I/O PORRST 32 3.3-V I RST 15 3.3-V I/O AWD 72 3.3-V I/O TCK 76 3.3-V I TDI 74 3.3-V I TDO 75 3.3-V O TEST 38 3.3-V I TMS 120 3.3-V I TMS2 121 3.3-V I TRST 37 3.3-V I FLTP1 134 NC FLTP2 133 NC V 135 3 ...

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... Table 2. Terminal Functions (continued) INTERNAL PULLUP/ (3) PULLDOWN SUPPLY VOLTAGE DIGITAL I/O (3.3 V) Digital I/O supply voltage SUPPLY GROUND CORE Core supply ground reference SUPPLY GROUND DIGITAL I/O Digital I/O supply ground reference Submit Documentation Feedback TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 DESCRIPTION 11 ...

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... TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 B512 Device-Specific Information Memory Figure 1 shows the memory map of the B512 device. Memory (4G Bytes) 0xFFFF_FFFF System Module Control Registers (512K Bytes) 0xFFF8_0000 0xFFF7_FFFF Peripheral Control Registers (512K Bytes) ...

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... NO YES (1) 32K YES 1.5K flash protection keys. These Submit Documentation Feedback TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 Table 3. MEMORY BASE ADDRESS STATIC MEM REGISTER CTL REGISTER MFBAHR0 and MFBALR0 MFBAHR1 and MFBALR1 MFBAHR2 and MFBALR2 ...

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... TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 Flash Read The B512 flash memory is configurable by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. The flash is addressed through memory selects 0 and 1. The flash external pump voltage (V and read) ...

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... FFF7_E000 0 x FFF7_E3FF 0 x FFF7_DC00 0 x FFF7_DFFF 0 x FFF7_D800 0 x FFF7_DBFF 0 x FFF7_D600 0 x FFF7_D7FF 0 x FFF7_D500 0 x FFF7_D5FF 0 x FFF7_D400 0 x FFF7_D4FF 0 x FFF7_C000 0 x FFF7_D3FF Submit Documentation Feedback TMS470R1B512 SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 PERIPHERAL SELECTS N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A ...

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... TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 Table 5. B512 Peripherals, System Module, and Flash Base Addresses (continued) CONNECTING MODULE RESERVED FLASH CONTROL REGISTERS MPU CONTROL REGISTERS Direct-Memory Access (DMA) The direct-memory access (DMA) controller transfers data to and from any specified location in the B512 memory map (except for restricted memory locations like the system control registers area) ...

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... DMA interrupt 1 GIO GIO interrupt B MibADC MibADC end Group 2 conversion RESERVED Table 7. Interrupt Priority (IEM and CIM) DEFAULT CIM INTERRUPT LEVEL/CHANNEL Submit Documentation Feedback TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 IEM CHANNEL ...

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... TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 Table 7. Interrupt Priority (IEM and CIM) (continued) MODULES INTERRUPT SOURCES RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED HECC2 HECC2 interrupt A HECC2 HECC2 interrupt B RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED ...

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... Converter (MibADC) Reference Guide (literature number SPNU206). 8. Table 8. MibADC Event Hookup Configuration SOURCE SELECT BITS FOR G1 OR EVENT (G1SRC[1:0] OR EVSRC[1:0 Submit Documentation Feedback TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 SIGNAL PIN NAME ADEVT HET18 HET19 RESERVED 19 ...

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... TMS470R1x JTAG Security Module (JSM) Reference Guide (literature number SPNU245) – TMS470R1x Memory Security Module (MSM) Reference Guide (literature number SPNU246) – TMS470 Peripherals Overview Reference Guide (literature number SPNU248) Errata Sheet – TMS470R1B512 TMS470 Microcontrollers Silicon Errata (literature number SPNZ141) 20 Submit Documentation Feedback www.ti.com ...

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... PACKAGE TYPE REVISION CHANGE Blank = Original FLASH MEMORY 512 = 512K-Bytes Flash Memory Figure 2. TMS470R1x Family Nomenclature Submit Documentation Feedback TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 OPTIONS TEMPERATURE T = – 105 – 125 C ...

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... TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 Device Identification Code Register The device identification code register identifies the silicon version, the technology family (TF), a ROM or flash device, and an assigned device-specific part number (see value is 0xn92Fh. ...

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... CCAD ADIN[0:15] T version Q version J (1) T version Q version , which is with respect CCAD SSAD Submit Documentation Feedback TMS470R1B512 –0 2.5 V (2) –0 4.1V –0 4. – 105 C – 125 C – 150 C – 150 C MIN NOM MAX UNIT 1 ...

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... TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 Electrical Characteristics over recommended operating free-air temperature range, T version (unless otherwise noted) PARAMETER V Input hysteresis hys All inputs except OSCIN V Low-level input voltage IL OSCIN only All inputs except ...

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... MIN for the respective pin 1.5 V LOAD C = 150-pF typical load-circuit capacitance L Figure 4. Test Load Circuit Submit Documentation Feedback TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 MIN TYP MAX (8) 10 (8) 300 (8) 300 = 3 3 ...

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... TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 Timing Parameter Symbology Timing parameter symbols have been created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: ...

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... The values of C1 and C2 should be provided by the resonator/crystal vendor. 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 Figure 5b. OSCOUT OSCIN External (A) C2 Clock Signal (toggling 0-1.8 V) Figure 5. Crystal/Clock Connection Submit Documentation Feedback TMS470R1B512 Figure 5a. The oscillator is a single-stage OSCOUT (b) 27 ...

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... TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 ZPLL AND CLOCK SPECIFICATIONS Timing Requirements for ZPLL Circuits Enabled or Disabled f Input clock frequency (OSC) t Cycle time, OSCIN c(OSC) t Pulse duration, OSCIN low w(OSCIL) t Pulse duration, OSCIN high ...

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... N is even and X is even or odd N is odd and X is even N is odd and X is odd and not 1 t w(COH) t w(COL) Figure 6. CLKOUT Timing Diagram t w(EOH) t w(EOL) Figure 7. ECLK Timing Diagram Submit Documentation Feedback TMS470R1B512 (1) (2) (3) MIN MAX 0.5t – t c(SYS) f 0.5t – t c(ICLK) f 0.5t + 0.5t – ...

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... TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 RST AND PORRST TIMINGS Timing Requirements for PORRST (see Figure low supply level when PORRST must be active during power up CCPORL CC V high supply level when PORRST must remain active during power up and become ...

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... TCK TMS TDI TDO t h(TCKf TDO) t c(JTAG) t su(TDI/TMS TCKr) t h(TCKr TDI/TMS) t d(TCKf TDO) Figure 9. JTAG Scan Timings Submit Documentation Feedback TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 MIN c(JTAG) MAX UNIT ...

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... TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 OUTPUT TIMINGS Switching Characteristics for Output Timings versus Load Capacitance (C (see Figure 10) t Rise time, CLKOUT, AWD, TDO r t Fall time, CLKOUT, AWD, TDO f t Rise time, SPInCLK, SPInSOMI, SPInSIMO ...

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... For more detailed information on the flash core sectors, see the flash program and erase section of this data sheet. (2) The 512K-byte programming time includes overhead of state machine. (1) (ICLK 80% 80% 20% Figure 11. CMOS-Level Inputs (1) (2) Submit Documentation Feedback TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 MIN c(ICLK 20% 0 MIN TYP ...

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... TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 SPIn MASTER MODE TIMING PARAMETERS SPIn Master Mode External Timing Parameters (CLOCK PHASE = 0, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input) NO Cycle time, SPInCLK c(SPC)M t Pulse duration, SPInCLK high (clock polarity = 0) ...

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... PS is the prescale value set in the SPInCTL1[12:5] register bits. c(ICLK) 100 ns Master Out Data Is Valid 6 Master In Data Must Be Valid Submit Documentation Feedback TMS470R1B512 SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 (1) (2) (3) (see Figure 13) MIN MAX 100 256t c(ICLK) 0.5t – ...

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... TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 SPIn SLAVE MODE TIMING PARAMETERS SPIn Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output) NO Cycle time, SPInCLK c(SPC)S t Pulse duration, SPInCLK high (clock polarity = 0) ...

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... PS = prescale value set in SPInCTL1[12:5]. c(SPC)S c(ICLK) (ICLK) (PS +1)t 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits. c(ICLK) 100 ns. Submit Documentation Feedback TMS470R1B512 SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 (1) (2) (3) (4) (see Figure 15) MIN MAX 100 256t c(ICLK) – ...

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... TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 SPInCLK (clock polarity = 0) SPInCLK (clock polarity = 1) SPInSOMI SPInSIMO Figure 15. SPIn Slave Mode External Timing (CLOCK PHASE = SPISOMI Data Is Valid 6 7 SPISIMO Data Must Be Valid Submit Documentation Feedback www ...

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... TXV) t su(RX SCCL) Data Valid Submit Documentation Feedback TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 (1) (2) (3) (BAUD + 1) IS ODD AND BAUD 0 MIN MAX – c(ICLK) c(ICLK) + 0.5t – t ...

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... TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 SCIn ISOSYNCHRONOUS MODE TIMINGS EXTERNAL CLOCK Timing Requirements for External Clock SCIn Isosynchronous Mode (see Figure 17) (3) t Cycle time, SCInCLK c(SCC) t Pulse duration, SCInCLK high w(SCCH) t Pulse duration, SCInCLK low ...

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... Delay time, CANnHRX pin to receive shift register d(CANnHRX) (1) These values do not include rise/fall times of the output buffer. 16/32-Bit RISC Flash Microcontroller HIGH-END TIMER (HET) TIMINGS NOTE: PARAMETER (1) Submit Documentation Feedback TMS470R1B512 SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 MIN MAX 15 5 UNIT ns ns ...

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... TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 MULTI-BUFFERED A-TO-D CONVERTER (MibADC) The multi-buffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that enhances the A-to-D performance by preventing digital switching noise on the logic circuitry, which could be present on ...

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... LSB 1 LSB Error(- 1/2 LSB Analog Input Value (LSB) 10 Figure 19. Differential Nonlinearity (DNL) Submit Documentation Feedback TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 Sample R Capacitor i MIN NOM 0.05 1 0.55 1.55 Differential Linearity Error(1/2 LSB ...

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... TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 The integral nonlinearity error shown in values on the actual transfer function from a straight line LSB = ( )/2 REFHI REFLO Figure 20. Integral Nonlinearity (INL) Error The absolute accuracy or total error of an MibADC as shown in difference between an analog value and the ideal midstep value ...

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... THERMAL RESISTANCE CHARACTERISTICS PARAMETER 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 Submit Documentation Feedback TMS470R1B512 C/W 43 6.5 45 ...

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... TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 This revision history highlights the changes made to the device-specific datasheet SPNS107. SPNS107 to SPNS107A Revised the Family Nomenclature drawing to add Q version of the temperature range. Revised "Absolute Maximum Ratings" table to add Q version of the temperature range. ...

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... PACKAGING INFORMATION (1) Orderable Device Status TMP470R1B512PGE PREVIEW TMS470R1B512PGET ACTIVE (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design ...

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PGE (S-PQFP-G144) 108 109 144 1 17,50 TYP 20,20 19,80 22,20 21,80 1,45 1,35 1,60 MAX NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 MTQF017A – ...

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