UPSD3254 STMICROELECTRONICS [STMicroelectronics], UPSD3254 Datasheet - Page 51

• Manufacturer Part Number: UPSD3254
• Description: Flash Programmable System Devices with 8032 Microcontroller Core
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Each RESET source will cause an internal reset
signal active. The CPU responds by executing an
internal reset and puts the internal registers in a
defined state. This internal reset is also routed as
an active low reset input to the PSD Module.
External Reset
The RESET pin is connected to a Schmitt trigger
for noise reduction. A RESET is accomplished by
holding the RESET pin LOW for at least 1ms at
power up while the oscillator is running. Refer to
AC spec on other RESET timing requirements.
Low V
An internal reset is generated by the LVR circuit
when the V
ter V
the RESET signal will remain asserted for 10ms
before it is released. On initial power-up the LVR
is enabled (default). After power-up the LVR can
be disabled via the LVREN Bit in the PCON Reg-
ister.
DD
DD
reaching back up to the reset threshold,
Voltage Reset
DD
drops below the reset threshold. Af-
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
Note: The LVR logic is still functional in both the
Idle and Power-down Modes.
The reset threshold:
This logic supports approximately 0.1V of hystere-
sis and 1µs noise-cancelling delay.
Watchdog Timer Overflow
The Watchdog timer generates an internal reset
when its 22-bit counter overflows. See Watchdog
Timer section for details.
USB Reset
The USB reset is generated by a detection on the
USB bus RESET signal. A single-end zero on its
upstream port for 4 to 8 times will set RSTF Bit in
UISTA register. If Bit 6 (RSTE) of the UIEN Regis-
ter is set, the detection will also generate the
RESET signal to reset the CPU and other periph-
erals in the MCU.
5V operation:
3.3V operation: 2.5V +/-0.2V
4V +/- 0.25V
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