W78E52BF-40 WINBOND [Winbond], W78E52BF-40 Datasheet - Page 4

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W78E52BF-40

Manufacturer Part Number
W78E52BF-40
Description
8-BIT MTP MICROCONTROLLER
Manufacturer
WINBOND [Winbond]
Datasheets
BLOCK DIAGRAM
FUNCTIONAL DESCRIPTION
The W78E52B architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports
111 different opcodes and references both a 64K program address space and a 64K data storage
space.
Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0 and 1. The T2CON register provides control functions for Timer 2.
RCAP2H and RCAP2L are used as reload/capture registers for Timer 2.
P1.0
P1.7
P3.0
P3.7
P4.3
P4.0
~
~
~
INT2
INT3
Port
1
Port
Port
3
4
Interrupt
UART
Port 3
Port 1
Timer
Timer
Timer
Port 4
Latch
Latch
Latch
2
0
1
XTAL1
Oscillator
XTAL2
PSW
Bus & Clock
Instruction
Sequencer
Controller
Decoder
ALE
ACC
&
T1
PSEN
ALU
Reset Block
Watchdog
SFR RAM
RAM & SFR
Timer
Address
256 bytes
- 4 -
ROM
RST
T2
B
Pointer
Stack
Power control
Vcc
Preliminary W78E52B
Vss
Temp Reg.
Incrementor
Addr. Reg.
DPTR
PC
Port 0
Latch
Port 2
Latch
Port
Port
2
0
P0.0
P0.7
P2.0
P2.7
~
~

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