OP2177ARM AD [Analog Devices], OP2177ARM Datasheet - Page 11

• Manufacturer Part Number: OP2177ARM
• Description: Precision Low Noise, Low Input Bias Current Operational Amplifiers
• Manufacturer: AD [Analog Devices]

Use an additional resistor in series with the inputs if the voltage
will exceed the supplies by more than 2.5 V. The value of the
resistor can be determined from the formula:
With the OP1177’s low input offset current of <1 nA max, placing
a 5 k resistor in series with both inputs adds less than 5 V to
input offset voltage and has a negligible impact on the overall
noise performance of the circuit.
5 k will protect the inputs to more than 27 V beyond either supply.
Refer to the THD + N section for additional information on
noise versus source resistance.
Output Phase Reversal
Phase reversal is defined as a change of polarity in the amplifier
transfer function. Many operational amplifiers exhibit phase reversal
when the voltage applied to the input is greater than the maxi-
mum common-mode voltage. In some instances this can cause
permanent damage to the amplifier. In feedback loops, it can
result in system lockups or equipment damage. The OP1177 is
immune to phase reversal problems even at input voltages beyond
the supplies.
Settling Time
Settling time is defined as the time it takes an amplifier output
to reach and remain within a percentage of its final value after
application of an input pulse. It is especially important in mea-
surement and control circuits where amplifiers buffer A/D inputs
or DAC outputs.
To minimize settling time in amplifier circuits, use proper bypassing
of power supplies and an appropriate choice of circuit components.
Resistors should be metal film types as these have less stray
capacitance and inductance than their wire-wound counterparts.
Capacitors should be polystyrene or polycarbonate types to
minimize dielectric absorption.
The leads from the power supply should be kept as short as
possible to minimize capacitance and inductance. The OP1177
has a settling time of about 45 s to 0.01% (1 mV) with a 10 V
step applied to the input in a noninverting unity gain.
Overload Recovery Time
Overload recovery is defined as the time it takes the output voltage
of an amplifier to recover from a saturated condition to its linear
response region. A common example is where the output voltage
R
V
S
IN
TIME – 400 s/DIV
500
V
S
V
IN
5
mA
V
OUT
V
A
SY
V
= 1
=
10V
demanded by the circuit’s transfer function lies beyond the maxi-
mum output voltage capability of the amplifier. A 10 V input
applied to an amplifier in a closed-loop gain of 2 will demand an
output voltage of 20 V. This is beyond the output voltage range of
the OP1177 when operating at 15 V supplies and will force the
output into saturation.
Recovery time is important in many applications, particularly where
the op amp must amplify small signals in the presence of large
transient voltages.
TPC 12 shows the positive overload recovery time of the OP1177.
The output recovers in less than 4 s after being overdriven by
more than 100%.
The negative overload recovery of the OP1177 is 1.4 s as seen
in TPC 13.
THD + Noise
The OP1177 has very low total harmonic distortion. This indicates
excellent gain linearity and makes the OP1177 a great choice for
high closed-loop gain precision circuits.
Figure 5 shows that the OP1177 has approximately 0.00025%
distortion in unity gain, the worst-case configuration for distortion.
Capacitive Load Drive
OP1177 is inherently stable at all gains and capable of driving
large capacitive loads without oscillation. With no external com-
pensation, the OP1177 will safely drive capacitive loads up to
1000 pF in any configuration. As with virtually any amplifier,
driving larger capacitive loads in unity gain requires additional
circuitry to assure stability.
In this case, a “snubber network” is used to prevent oscillation
and reduce the amount of overshoot. A significant advantage of
this method is that it does not reduce the output swing because
the resistor R
200mV
0.0001
0.001
0.01
0.1
20
+
S
is not inside the feedback loop.
1k
R1
OP1177/OP2177/OP4177
100
2
3
FREQUENCY – Hz
100k
4
7
R2
V
V+
OP1177
1
1k
V
R
BW = 22kHz
10k
SY
L
= 10k
=
15V
V
OUT
6k