ATA5724 ATMEL [ATMEL Corporation], ATA5724 Datasheet - Page 16

• Manufacturer Part Number: ATA5724
• Description: UHF ASK/FSK Receiver
• Manufacturer: ATMEL [ATMEL Corporation]

8.6
Figure 8-7.
Figure 8-8.
16
Digital Signal Processing
Data_out (DATA)
Data_out (DATA)
ATA5723/ATA5724/ATA5728
Clock bit-check
counter
Dem_out
Synchronization of the Demodulator Output
Debouncing of the Demodulator Output
Dem_out
The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different ways and
as a result converted into the output signal data. This processing depends on the selected
baud-rate range (BR_Range).
extended clock cycle T
state only after T
is always an integral multiple of T
The minimum time period between two edges of the data signal is limited to t
implies an efficient suppression of spikes at the DATA output. At the same time it limits the max-
imum frequency of edges at DATA. This eases the interrupt handling of a connected
microcontroller.
The maximum time period for DATA to stay low is limited to T
employed to ensure a finite response time in programming or switching off the receiver via pin
DATA. T
data stream.
receiver has switched to receiving mode.
T
t
XClk
DATA_min
DATA_L_max
Figure 8-9 on page 17
t
XClk
ee
is therefore longer than the maximum time period indicated by the transmitter
has elapsed. The edge-to-edge time period t
XClk
. This clock is also used for the bit-check counter. Data can change its
t
DATA_min
Figure 8-7
XClk
.
gives an example where Dem_out remains Low after the
t
ee
illustrates how Dem_out is synchronized by the
t
ee
ee
t
DATA_min
DATA_L_max
of the Data signal as a result
t
ee
ee
. This function is
T
9106E–RKE–07/08
DATA_min
. This