XC6119 TOREX [Torex Semiconductor], XC6119 Datasheet - Page 8

• Manufacturer Part Number: XC6119
• Description: Voltage Detector with Delay Time Adjustable
• Manufacturer: TOREX [Torex Semiconductor]

●Release Delay Time Chart
8/16
Delay Capacitance [Cd]
* The release delay time values above are calculate by using formula (2).
*1: The release delay time (t
⑧
⑤ While the input pin voltage increases more than 0.7V and it reaches to the release voltage level (V
⑥ When the input pin voltage continues to increase more than 0.7V up to the release voltage level (= V
⑦ While the input pin voltage becomes equal to the release voltage or higher and keeps the detect voltage or higher, the delay
The release delay time can also be briefly calculated with the formula (2) because the delay resistance is 2.0MΩ(TYP.) and the
delay capacitance pin threshold voltage is VIN /2 (TYP.)
* Note that the release delay time may remarkably be short when the delay capacitance is not discharged to the ground (=V
■OPERATIONAL EXPLANATION (Continued)
As an example, presuming that the delay capacitance is 0.68μF, t
level because time described in ③ is short.
output voltage (V
transistor for the delay capacitance discharge will be turned OFF, and the delay capacitance will be started discharging via a
delay resistor (Rdelay). The internal circuit, which uses the delay capacitance pin as power input, will operate as a
hysteresis comparator (Rise Logic Threshold: V
higher than the detect voltage (V
capacitance (Cd) will be charged up to the input pin voltage. When the delay capacitance pin voltage (V
delay capacitance pin threshold voltage (V
time which ranges from V
can be given by the formula (1).
While the input pin voltage is higher than the detect voltage (V
“High”(=V
XC6119
0.022
0.047
(μF)
0.01
0.22
0.47
0.1
1
IN
) level.
OUT
Series
) maintains the “Low” level.
DR
) is influenced by the release capacitance (Cd).
IN
Release Delay Time [t
=V
DF
* In = a natural logarithm
* R
IN
+V
t
> V
DR
DELAY
HYS
=
DF
to the V
－
).
1380
is 2.0MΩ(TYP.)
13.8
30.4
64.9
138
304
649
(ms)
2.0
R
TCD
DELAY
×
t
DR
), the output voltage changes into the “High” (=V
10
OUT
TLH
=R
×
DR
6
×
=V
DELAY
Cd
] (TYP.)
of “High” level (especially when the Cd pin is not connected: t
0.68
TCD
×
×
In (1
, Fall Logic Threshold: V
×
Cd
10
－
×
-6
VTCD / VIN) +t
0.69
×
DR
0.69=938(ms)
is :
IN
…
Release Delay Time [t
> V
(2)
DF
), therefore, the output voltage maintains the
DR0
THL
…(1)
1100 ~ 1660
11.0 ~ 16.6
24.3 ~ 36.4
51.9 ~ 77.8
110 ~ 166
243 ~ 364
519 ~ 778
=V
(ms)
SS
) while the input pin voltage keeps
DR
] (MIN. ~ MAX.) *1
IN
) level. t
IN
＜V
DF
DF
CD
+V
+ V
DR
) reaches to the
HYS
HYS
is defined as
), the
), the N-ch
DR0
). t
SS
DR
)