AK5381ET AKM [Asahi Kasei Microsystems], AK5381ET Datasheet - Page 12

no-image

AK5381ET

Manufacturer Part Number
AK5381ET
Description
24Bit 96kHz ?? ADC
Manufacturer
AKM [Asahi Kasei Microsystems]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AK5381ET
Manufacturer:
AKM
Quantity:
20 000
Part Number:
AK5381ET-E2
Manufacturer:
KYOCERA
Quantity:
1 000
Part Number:
AK5381ET-E2
Manufacturer:
AKM
Quantity:
20 000
ASAHI KASEI
MCLK (256fs/384fs/512fs), SCLK and LRCK (fs) clocks are required in slave mode. The LRCK clock input must be
synchronized with MCLK, however the phase is not critical. Table 1 shows the relationship of typical sampling frequency
and the system clock frequency. MCLK frequency, SCLK frequency, HPF (ON or OFF), the input level (CMOS or TTL)
and master/slave are selected by CKS2-0 pins as shown in Table 2.
All external clocks (MCLK, SCLK and LRCK) must be present unless PDN pin = “L”. If these clocks are not provided,
the AK5381 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not
present, place the AK5381 in power-down mode (PDN pin = “L”). In master mode, the master clock (MCLK) must be
provided unless PDN pin = “L”.
Note: SDTO outputs 16bit data at SCLK=32fs.
Note: The AK5381 does not support TTL interface at 96kHz.
Two kinds of data formats can be chosen with the DIF pin (Table 3). In both modes, the serial data is in MSB first, 2’s
compliment format. The SDTO is clocked out on the falling edge of SCLK. The audio interface supports both master and
slave modes. In master mode, SCLK and LRCK are output with the SCLK frequency fixed to 64fs and the LRCK
frequency fixed to 1fs.
MS0200-E-02
System Clock
Audio Interface Format
CKS2
H
H
H
H
L
L
L
L
CKS1
H
H
H
H
L
L
L
L
Mode
0
1
44.1kHz
32kHz
48kHz
96kHz
CKS0
fs
H
H
H
H
L
L
L
L
DIF pin
H
L
Input Level
11.2896MHz
12.288MHz
24.576MHz
8.192MHz
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
TTL*
256fs
24bit, I
24bit, MSB justified
Table 1. System Clock Example
Table 3. Audio Interface Format
OPERATION OVERVIEW
2
SDTO
S Compatible
HPF
OFF
Table 2. Mode Select
ON
ON
ON
ON
ON
ON
16.9344MHz
12.288MHz
18.432MHz
36.864MHz
384fs
Master/Slave
- 12 -
Master
Master
Master
Master
Slave
Slave
Slave
MCLK
LRCK
H/L
L/H
22.5792MHz
16.384MHz
24.576MHz
Reserved
512fs
N/A
256/384fs (∼ 96kHz)
512/768fs (∼ 48kHz)
256/384fs (∼ 96kHz)
512/768fs (∼ 48kHz)
256fs/384/512/768fs
≥ 48fs or 32fs
≥ 48fs or 32fs
256fs (∼ 96kHz)
512fs (∼ 48kHz)
384fs (∼ 96kHz)
768fs (∼ 48kHz)
SCLK
(∼ 48kHz)
MCLK
33.8688MHz
24.576MHz
36.864MHz
768fs
N/A
Figure 1
Figure 2
Figure
≥ 48fs or 32fs
≥ 48fs or 32fs
≥ 48fs or 32fs
SCLK
64fs
64fs
64fs
64fs
[AK5381]
2006/01

Related parts for AK5381ET