AK4359A AKM [Asahi Kasei Microsystems], AK4359A Datasheet - Page 24

• Manufacturer Part Number: AK4359A
• Description: 106dB 192kHz 24-Bit 8ch DAC
• Manufacturer: AKM [Asahi Kasei Microsystems]

MS1010-E-01
(2) I
The AK4359A supports the fast-mode I
Figure 16
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition
START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit which is a data direction
bit (R/W)
(device address bit). The bit identify the specific device on the bus. The hard-wired input pin (CAD0 pin) set them. If the
slave address match that of the AK4359A and R/W bit is “0”, the AK4359A generates the acknowledge and the write
operation is executed. If R/W bit is “1”, the AK4359A generates the not acknowledge since the AK4359A can be only a
slave-receiver. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during
the acknowledge clock pulse
The second byte consists of the address for control registers of the AK4359A. The format is MSB first, and those most
significant 3-bits are fixed to zeros
first, 8bits
terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is
HIGH defines a STOP condition
The AK4359A is capable of more than one byte write operation by one sequence. After receipt of the third byte, the
AK4359A generates an acknowledge, and awaits the next data. The master can transmit more than one byte instead of
terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal 5bits address
counter is incremented by one, and the next data is taken into next address automatically. If the addresses exceed 1FH
prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be
overwritten.
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW
condition.
2
C-bus Control Mode (I2C pin = “H”)
(Figure
shows the data transfer sequence at the I
(Figure
SDA
17). The most significant six bits of the slave address are fixed as “001001”. The next one bit are CAD0
19). The AK4359A generates an acknowledge after each byte is received. A data transfer is always
D7
0
0
S
T
A
R
T
S
(Figure
Slave
Address
Figure 16. Data transfer sequence at the I
(Figure
D6
(Figure
0
0
Figure 19. Byte structure after the second byte
21).
R/W
(This CAD0 should match with CAD0 pin)
2
A
C
K
C-bus system (max: 400kHz).
20).
18). Those data after the second byte contain control data. The format is MSB
Sub
Address(n)
D5
1
0
Figure 18. The second byte
Figure 17. The first byte
2
C-bus mode. All commands are preceded by a START condition. A
A
C
K
A4
D4
0
- 24 -
Data(n)
(Figure
A3
D3
0
A
C
K
Data(n+1)
22) except for the START and the STOP
2
A2
D2
C-bus mode
1
A
C
K
CAD0
A1
D1
A
C
K
Data(n+x)
R/W
A0
D0
(Figure
A
C
K
S
T
O
P
P
20). After the
[AK4359A]
2008/10