AK4371VN AKM [Asahi Kasei Microsystems], AK4371VN Datasheet - Page 20

• Manufacturer Part Number: AK4371VN
• Description: DAC with built-in PLL & HP-AMP
• Manufacturer: AKM [Asahi Kasei Microsystems]

When PLL reference clock input is LRCK or BICK pin, the sampling frequency is selected by FS3-0 bits. (Table 6)
■
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In master mode (M/S bits = “1”), LRCK and BICK pins output “L” before the PLL is locked by setting PMPLL =
PMDAC bits = “0”
MCKO bit = “0”, MCKO pin outputs “L”. After the PLL is locked, LRCK and BICK start to output the clocks (Table 7).
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In slave mode (M/S bits = “0”), an invalid clock is output from MCKO pin when MCKO bit = “1”, before the PLL is
locked by setting PMPLL = PMDAC bits = “0”
locked, MCKO starts to output the clocks (Table 9).
MS0596-E-00
MCKI pin
MCKO pin MCKO bit = “0”: “L”
BICK pin
LRCK pin
MCKI pin
MCKO pin MCKO bit = “0”: “L”
BICK pin
LRCK pin
PLL Unlock State
Others
Mode
0
1
2
3
4
Table 6. Setting of Sampling Frequency (PLL reference clock input is LRCK or BICK pin)
MCKO bit = “1”: Output
Power Up
(PMDAC bit= PMPLL bit= “1”)
Refer to Table 4.
BF bit = “1”: 64fs output
BF bit = “0”: 32fs output
Output
Power Up
(PMDAC bit= PMPLL bit= “1”)
Refer to Table 4.
MCKO bit = “1”: Output
Input
Input
FS3 bit
“1”. At that time, MCKO pin outputs an abnormal frequency clock at MCKO bit = “1”. When
1
1
1
1
1
Table 7. Clock Operation in Master mode (PLL mode)
Table 8. Clock Operation in Slave mode (PLL mode)
FS2 bit
0
0
0
0
1
Others
FS1 bit
Power Down
(PMDAC bit= PMPLL bit= “0”)
Input or
fixed to “L” or “H” externally
“L”
“L”
“L”
Power Down
(PMDAC bit= PMPLL bit= “0”)
Input or
fixed to “L” or “H” externally
“L”
Fixed to “L” or “H” externally
Fixed to “L” or “H” externally
Master Mode (M/S bit = “1”)
“1”. When MCKO bit = “0”, MCKO pin outputs “L”. After the PLL is
Slave Mode (M/S bit = “0”)
0
0
1
1
0
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FS0 bit
0
1
0
1
0
Sampling Frequency Range
32kHz < fs ≤ 48kHz
24kHz < fs ≤ 32kHz
16kHz < fs ≤ 24kHz
12kHz < fs ≤ 16kHz
8kHz ≤ fs ≤ 12kHz
N/A
PLL Unlock
Refer to Table 4.
MCKO bit = “0”: “L”
MCKO bit = “1”: Unsettling
“L”
“L”
PLL Unlock
Refer to Table 4.
MCKO bit = “0”: “L”
MCKO bit = “1”: Unsettling
Input or
Fixed
externally
Input or
Fixed
externally
to
to
“L”
“L”
(default)
or
or
[AK4371]
“H”
“H”
2007/04