AK4388A AKM [Asahi Kasei Microsystems], AK4388A Datasheet - Page 12

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AK4388A

Manufacturer Part Number
AK4388A
Description
192kHz 24-Bit 2ch ?? DAC
Manufacturer
AKM [Asahi Kasei Microsystems]
Datasheet

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The AK4388A must be reset once by bringing the RSTN pin = “L” upon power-up. The AK4388A is powered up and the
internal timing starts clocking by LRCK “↑” after exiting reset by MCLK. The AK4388A is in reset state until LRCK is
input.
The AK4388A is placed in the power-down mode by bringing the RSTN pin “L” and the registers are initialized. The
analog outputs go to VCOM (VDD/2). Since click noise occurs at the edge of the RSTN signal, the analog output should
be muted externally if click noise aversely affects system application.
Notes:
MS1008-E-02
System Reset
Power ON/OFF timing
Internal
State
DZF
DAC In
DAC Out
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are VCOM (VDD/2) in power-down mode.
(3) Click noise occurs at the edge of RSTN signal. This noise is output even if “0” data is input.
(4) Mute the analog output externally if the click noise (3) influences the system application.
(5) DZF pins are “L” in the power-down mode (RSTB pin = “L”).
External
RSTN pin
Power
(Digital)
(Analog)
Mute
The timing example is shown in this figure.
(2)
(4)
(3)
Figure 9. Power-down/up Sequence Example
Mute ON
“0”data
Normal Operation
- 12 -
GD
(1)
“0”data
GD
(3)
(5)
Reset
Mute ON
[AK4388A]
(2)
2010/09

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