AK4392 AKM [Asahi Kasei Microsystems], AK4392 Datasheet - Page 18
AK4392
Manufacturer Part Number
AK4392
Description
High Performance 120dB Premium 32-Bit DAC
Manufacturer
AKM [Asahi Kasei Microsystems]
Datasheet
1.AK4392.pdf
(41 pages)
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MCLK= 256fs/384fs supports sampling rate of 30kHz~108kHz
DR and S/N will degrade by approximately 3dB as compared to when MCLK= 512fs/768fs.
[2] DSD Mode
The external clocks, which are required to operate the AK4392, are MCLK and DCLK. MCLK should be synchronized
with DCLK but the phase is not critical. The frequency of MCLK is set by DCKS bit.
The AK4392 is automatically placed in reset state when MCLK is stopped during a normal operation (PDN pin =“H”),
and the analog output becomes Hi-Z. After exiting system reset (PDN pin =“L”→“H”) at power-up and other situations,
the AK4392 is in power-down mode until MCLK is supplied.
MS1045-E-02
176.4kHz
192.0kHz
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
LRCK
fs
Table 4. System Clock Example (Parallel Control Mode) (N/A: Not available)
Table 5. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz)
22.5792
24.5760
128fs
N/A
N/A
N/A
N/A
N/A
DCKS bit
0
1
33.8688
36.8640
256fs/384fs
512fs/768fs
192fs
N/A
N/A
N/A
N/A
N/A
MCLK
MCLK Frequency
Table 6. System Clock (DSD Mode)
512fs
768fs
11.2896
12.2880
22.5792
24.5760
8.1920
256fs
N/A
N/A
- 18 -
MCLK (MHz)
DR,S/N
12.2880
16.9344
18.4320
33.8688
36.8640
117dB
120dB
(Table
384fs
N/A
N/A
DCLK Frequency
5). But, when the sampling rate is 30kHz~54kHz,
64fs
64fs
16.3840
22.5792
24.5760
512fs
N/A
N/A
N/A
N/A
(default)
24.5760
33.8688
36.8640
768fs
N/A
N/A
N/A
N/A
36.8640
1152fs
N/A
N/A
N/A
N/A
N/A
N/A
[AK4392]
2009/04
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