78P2343-IEL TERIDIAN [Teridian Semiconductor Corporation], 78P2343-IEL Datasheet
78P2343-IEL
Related parts for 78P2343-IEL
78P2343-IEL Summary of contents
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... The transmitter generates a signal that meets the standard pulse shape requirements. 78P2343JAT includes optional B3ZS/HDB3 ENDEC with a receive line code violation detector, loop-back modes, Loss of Signal detector, clock polarity selection, and the ability to receive a DSX3 monitor signal. STANDARDS Telcordia GR-499-CORE and GR-253-CORE ITU-T G ...
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... Page The jitter tolerance of 78P2343JAT meets the requirements of ITU-T G.823 for E3 rates; the for connection requirements of ITU-T G.824 and Telcordia GR-499 (Cat I and II) for DS3 rates; and the requirements of Telcordia GR-253 for STS1 rates. ...
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... Source shown below. Note that redundant channel modes can only be activated using the serial interface. LPBKx pin The Register 2005 Teridian Semiconductor Corporation 78P2343JAT 3-port E3/DS3/STS-1 LIU with Jitter Attenuator Transmitter #1 00 Receiver LLBKA,B(1) ...
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... HDB3. 3) Code violation: Even number of bipolar pulses (B) detected between bipolar violation pulses (V). When the ENDEC is disabled, the 78P2343JAT outputs a dual rail data stream via the RPOSx and RNEGx pins. In this mode, the Framer/Mapper providing the ENDEC function typically detects Line Code Violations ...
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... JABW bit depends on which line-rate is selected through the MSL0 pin DS3 mode is selected, the default state is ‘0’. If STS1 mode is selected, the default state is ‘1’. 2005 Teridian Semiconductor Corporation 78P2343JAT 3-port E3/DS3/STS-1 LIU with Jitter Attenuator Jitter Attenuator can ...
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... Page SERIAL CONTROL INTERFACE The serial port controlled register allows a generic controller to interface with the 78P2343JAT used for mode settings, diagnostics and test, and the retrieval of status and performance information. The serial interface consists of four pins: Chip Select (CS), Serial Clock (SCK), Serial Data In (SDI), and Serial Data Out (SDO) ...
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... FERR <1> <1> <0> <1> JAEN JASL JLBK <0> <X> <X> <0> <0> <0> <0> <0> <0> <0> 2005 Teridian Semiconductor Corporation 78P2343JAT 3-port E3/DS3/STS-1 LIU with Jitter Attenuator Bit 2 Bit 1 Bit 0 Read/ Sub-Address Write SA[1] SA[0] R/W* Bit 3 Bit 2 Bit 1 RCLKP TCLKP -- <0> <0> JAER RXER -- <0> <1> <0> <0> <0> ...
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... E3/DS3/STS-1 LIU with Jitter Attenuator REGISTER DESCRIPTION LEGEND TYPE DESCRIPTION R/O Read only GLOBAL REGISTERS ADDRESS 0-0: MASTER CONTROL REGISTER DFLT BIT NAME TYPE VALUE 7 REGEN R DS3 R R ENDECB R RCLKP R TCLKP R RSVD R SRST R/W 0 Page (continued) ...
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... When set, loss of receive signal (as indicated by the LOS bit) will cause an interrupt to be flagged. Transmitter Error Event: When set, transmitter fault (as indicated by the TXNW bit) will cause an interrupt to be flagged. 2005 Teridian Semiconductor Corporation 78P2343JAT 3-port E3/DS3/STS-1 LIU with Jitter Attenuator DESCRIPTION Rev 2.2 ...
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... E3/DS3/STS-1 LIU with Jitter Attenuator REGISTER DESCRIPTION PORT-SPECIFIC REGISTERS For PA[3: 1-3 only. Accessing a register with port address greater than 3 constitutes an invalid command, and the read/write operation will be ignored. ADDRESS N-0: MODE CONTROL REGISTER DFLT BIT NAME TYPE VALUE 7 PDTX R PDRX ...
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... Transmitter Not-Working Indication Transmitter Transmitter not working Reserved Signal Low Indication Receive signal level Receive signal level too low / Loss of signal 2005 Teridian Semiconductor Corporation 78P2343JAT 3-port E3/DS3/STS-1 LIU with Jitter Attenuator DESCRIPTION Rev 2.2 ...
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... E3/DS3/STS-1 LIU with Jitter Attenuator REGISTER DESCRIPTION ADDRESS N-3: JITTER ATTENUATOR CONTROL REGISTER DFLT BIT NAME TYPE VALUE 7 JAEN R JASL R JLBK R RSVD R/W 0 ESP 3:2 R/W 11 [1:0] 1 RSVD R JABW R/W X Page (continued) Jitter Attenuator Enable Disables jitter attenuation function ...
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... TPOSx is high. When ENDECB =’0’, this pin is ignored. Transmitter Clock Input: CIS This signal is used to latch the respective TPOSx and TNEGx signals into the 78P2343JAT. Line Out: Differential AMI Outputs. Requires a 1:2CT center-tapped A transformer and a shunt termination resistor. See APPLICATION INFORMATION section for more info. ...
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... E3/DS3/STS-1 LIU with Jitter Attenuator PIN DESCRIPTION (continued) RECEIVER PINS NAME PIN TYPE 57 CKREF 27, 35 RCLKx 43 28, 36 RNEGx 44 29, 37 RPOSx 45 96, 90 LINPx 83 95, 89 LINNx 82 Page DESCRIPTION Reference Clock Input: This clock should be from a clean source ( 20 ppm) and match the ...
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... This pin is normally high when the INPOL bit is ‘0’ (default), and CO normally low when the INPOL bit is ‘1’. When an interrupt event occurs (as defined in the Interrupt Control Register description), the respective INTRx pin will change state. 2005 Teridian Semiconductor Corporation 78P2343JAT 3-port E3/DS3/STS-1 LIU with Jitter Attenuator Rev 2.2 ...
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... E3/DS3/STS-1 LIU with Jitter Attenuator PIN DESCRIPTION (continued) SERIAL-PORT PINS NAME PIN TYPE CS 65 SCK 66 SDI 68 SDO 67 COZ POWER AND GROUND PINS It is recommended that all supply pins be connected to a single power supply plane and all ground pins be connected to a single ground plane. ...
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... Iddr JAT Disabled DS3/E3 mode Iddt JAT Enabled: JAT Disabled: DS3/E3 mode Iddx JAT Enabled: JAT Disabled: PDTX = 1, PDRX = 1 Iddq 2005 Teridian Semiconductor Corporation 78P2343JAT 3-port E3/DS3/STS-1 LIU with Jitter Attenuator MIN NOM MAX 265 288 246 267 : 118 128 97 ...
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... E3/DS3/STS-1 LIU with Jitter Attenuator ELECTRICAL SPECIFICATIONS ANALOG PINS CHARACTERISTICS: The following table is provided for informative purpose only. Not tested in production. PARAMETER LINPx and LINNx Common-Mode Bias Voltage LINPx and LINNx Differential Input Impedance PORB Input Impedance DIGITAL I/O CHARACTERISTICS: ...
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... SYMBOL CONDITIONS Vtil Vtih Rtiz SYMBOL CONDITIONS Vol Iol = 8mA Voh Ioh = -8mA 20pF; (20-80%) L Cout Rsrc Iz Type COZ only 2005 Teridian Semiconductor Corporation 78P2343JAT 3-port E3/DS3/STS-1 LIU with Jitter Attenuator MIN NOM MAX 0.8 2.0 30 MIN NOM MAX 0.4 2 UNIT V ...
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... E3/DS3/STS-1 LIU with Jitter Attenuator ELECTRICAL SPECIFICATIONS SERIAL-PORT TIMING CHARACTERISTICS: PARAMETER CS or SDI to SCK setup time CS or SDI to SCK hold time SCK to SDO propagation delay SCK Frequency SEN t su SCK SDI X 1 SA0 SA1 SA2 SDO Z SEN ...
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... TIMING DIAGRAM: Transmitter Waveforms (E3/DS3/STS-1) TCLK TCLKP=LOW TCLK TCLKP=HIGH TTDPS TPOS TNEG Page (continued) SYMBOL CONDITIONS TTC/TTCF TTDxS TTDxH TTCF TTC TTDPH TTDNH TTDNS 2005 Teridian Semiconductor Corporation 78P2343JAT 3-port E3/DS3/STS-1 LIU with Jitter Attenuator MIN NOM MAX 40 60 2.5 2.5 UNIT % ns ns Rev 2.2 ...
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... E3/DS3/STS-1 LIU with Jitter Attenuator ELECTRICAL SPECIFICATIONS RECEIVE TIMING CHARACTERISTICS: PARAMETER CKREF Duty Cycle CKREF Frequency Stability RCLK Duty Cycle Data Propagation Delay Receive Loss of Signal Assert Timing Receive Loss of Signal De-assert Timing Note 1: At least a 100 S of software delay must be added after STS-1 LOS de-assertion to be compliant with the ANSI T1 ...
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... Measured at 0ft of terminated 75ohm cable with LBO pin held high (enabled). Ratio of amplitudes of positive and negative pulses measured at pulse peaks. PRBS15 pattern band-limited to 207.36MHz. 2005 Teridian Semiconductor Corporation 78P2343JAT 3-port E3/DS3/STS-1 LIU with Jitter Attenuator MIN TYP MAX 900 1000 1100 0.95 1 ...
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... E3/DS3/STS-1 LIU with Jitter Attenuator ELECTRICAL SPECIFICATIONS E3 TRANSMIT PULSE TEMPLATE 0.2 0.1 1.0 0.1 0.2 0.5 0.1 0 0.1 Page (continued 8.65 ns 14.55 ns 12.1 ns 24.5 ns 0.2 29.1 ns 2005 Teridian Semiconductor Corporation 0.1 0.1 Rev 2.2 ...
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... Time axis range (UI) -0.85 < T < -0.68 -0.68 < T < 0.36 0.36 < T < 1.4 -0.85 < T < -0.36 -0.36 < T < 0.36 0.36 < T < 1.4 Page (continued) 0 0.5 Time, Unit Intervals Normalized amplitude equation UPPER CURVE 0.03 0.03 + 0.5{1+sin[(pi/2)(1+T/0.34)]} -1.84(T-0.36) 0.08+0.407 e LOWER CURVE -0.03 -0.03 + 0.5{1+sin[(pi/2)(1 + T/0.18)]} -0.03 2005 Teridian Semiconductor Corporation 78P2343JAT 3-port E3/DS3/STS-1 LIU with Jitter Attenuator 1 1.5 Rev 2.2 ...
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... E3/DS3/STS-1 LIU with Jitter Attenuator ELECTRICAL SPECIFICATIONS STS-1 TRANSMIT PULSE TEMPLATE 1.2 1 0.8 0.6 0.4 0.2 0 -0.2 -1 -0.5 STS-1 (Transmit template specs) Time axis range (T) -0.85 < T < -0.68 -0.68 < T < 0.26 0.26 < T < 1.4 -0.85 < T < -0.38 -0.38 < T < 0.36 0.36 < T < 1.4 Page (continued) 0 0.5 Time, Unit Intervals Normalized amplitude equation (A) UPPER CURVE ...
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... Transmitter Output Jitter Note: Filters defined by standards are used for all testing Page (continued) 20dB/decade f1 CONDITION 800 kHz 10 kHz to 800 kHz 2005 Teridian Semiconductor Corporation 78P2343JAT 3-port E3/DS3/STS-1 LIU with Jitter Attenuator Measured Jitter Amplitude f2 MIN NOM MAX 0.15 0.08 ...
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... E3/DS3/STS-1 LIU with Jitter Attenuator ELECTRICAL SPECIFICATIONS TRANSMIT MONITOR SPECIFICATIONS The transmit monitor function looks at the signals on the LOUTPx and LOUTNx pins and checks for the existence of a valid signal. The monitor detects the peak of the transmitted signal at the LOUTPx and LOUTNx pins and checks that it is between V window, the TXNW signal is low ...
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... Normal receive mode b) Remote loopback mode Maximum ratio of Interference Power -8 to Signal Power for BER < With 0ft cable from DSX b) With 450ft cable from DSX 2005 Teridian Semiconductor Corporation 78P2343JAT 3-port E3/DS3/STS-1 LIU with Jitter Attenuator MIN TYP MAX 90 850 25 ...
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... E3/DS3/STS-1 LIU with Jitter Attenuator ELECTRICAL SPECIFICATIONS E3 – RECEIVER SPECIFICATIONS (Transformer-coupled) PARAMETER CONDITION MON=0 (See Note 1) Peak Differential Input Amplitude, LINPx and LINNx MON=1 (See Note 2) MON=0. Flat-loss Tolerance All valid cable lengths. With 100Hz-800kHz filter: Receive Clock Jitter ...
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... ELECTRICAL SPECIFICATIONS RECEIVER JITTER TOLERANCE The 78P2343JAT receive jitter tolerance exceeds all specifications as shown on the graph below. PARAMETER Receiver High Frequency Jitter Tolerance Jitter Tolerance: 78P234x vs. Standards JAT enabled Page (continued) CONDITION > ...
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... E3/DS3/STS-1 LIU with Jitter Attenuator ELECTRICAL SPECIFICATIONS RECEIVER JITTER TRANSFER FUNCTION The receiver clock recovery loop characteristics are such that the receiver has the following transfer function. When the Jitter Attenuator (JAT) is enabled in the receive or transmit path, the receiver or transmitter will exhibit a jitter transfer as shown in the graph and table below ...
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... THERMAL INFORMATION PACKAGE Standard 100-pin JEDEC LQFP (78P2343JAT-IGT) Exposed Pad 100-pin JEDEC LQFP (78P2343JAT-IEL) SCHEMATICS For schematics, recommended transformer part numbers, etc. please check Teridian Semiconductor's website or contact your local sales representative for the latest application note(s) and/or demo board manuals. ...
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... Jitter Attenuator MECHANICAL SPECIFICATIONS (Top View) 15.7 (0.618) 16.3 (0.641) PIN No. 1 Indicator Page 15.7 (0.618) 16.3 (0.641) 13.8 (0.543) SQ 14.2 (0.559) 0.50 TYP. 0.60 (0.024) TYP. (0.0197) 0.18( 0.007) 0.27 (0.011) IGT 78P2343JAT- Mechanical Specification 100-pin TQFP (JEDEC LQFP) 2005 Teridian Semiconductor Corporation 0.00(0) 1.40 (0.055) 0.20 (0.008) 1.60 (0.063) Rev 2.2 ...
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... REF. 100 10.000 MAX. MAX. 1.600 1.400 +/- 0.050 0.500 IEL 78P2343JAT- Mechanical Specification 100-pin Exposed Pad LQFP (JEDEC LQFP) 2005 Teridian Semiconductor Corporation 78P2343JAT 3-port E3/DS3/STS-1 LIU with Jitter Attenuator 1 0.100 +/- 0.050 0.600 +/- 0.150 Rev 2.2 ...
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... JEDEC LQFP w/ Exposed Solder Pad, No Jitter Attenuator Tape & Reel option Lead-free option Page 78P2343JAT 100-pin TQFP (JEDEC LQFP) ORDER NUMBER 78P2343JAT-IGT /A07 78P2343-IGT /A07 78P2343JAT-IEL /A07 78P2343-IEL /A07 append ‘R’ append ‘/F’ 2005 Teridian Semiconductor Corporation 75 VCC 74 VCC VCC 73 ...
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... July 29, 2005 Changed company name and logo from TDK to Teridian Changed Package Marking for non-JAT 78P2343 ordering option This product is sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement and limitation of liability. Teridian Semiconductor Corporation (TSC) reserves the right to make changes in specifications at any time without notice ...