SP691ANEB SIPEX [Sipex Corporation], SP691ANEB Datasheet - Page 3

• Manufacturer Part Number: SP691ANEB
• Description: Evaluation Board Manual
• Manufacturer: SIPEX [Sipex Corporation]

Pin 7 – OSC IN – External Oscillator Input.
When OSC SEL is unconnected or driven high,
a 10 A pull-up connects from V
the internal oscillator sets the reset and watchdog
timeout periods, and OSC IN selects between
fast and slow watchdog timeout periods. When
OSC SEL is driven low, the reset and watchdog
timeout periods may be set either by a capacitor
from OSC IN to ground or by an external clock
at OSC IN.
Pin 8 – OSC SEL – Oscillator Select. When OSC
SEL is unconnected or driven high, the internal
oscillator sets the reset and watchdog timeout
periods. When OSC SEL is low, the external
oscillator input (OSC IN) is enabled. OSC SEL
has a 10 A pull-up.
Pin 9 – PFI – Power-Fail Input. This is the
non-inverting input to the power-fail comparator.
When PFI is less than 1.25V, PFO_N goes low.
Connect PFI to GND or VOUT when not used.
Connect external divider R1 & R2 to Probe Pins
and connect Unregulated Voltage to UNREG
for Power Fail monitoring.
Pin 10 – PFO – Power-Fail Output. This is the
output of the power-fail comparator. PFO, goes
low when PFI is less than 1.25V. This is an
uncommitted comparator, and has no effect on
any other internal circuitry.
Pin 11 – WDI – Watchdog Input. WDI is a
three-level input. If WDI remains either high or
low for longer than the watchdog timeout
period, WDO goes low and reset is asserted for
the reset timeout period. WDO remains low
until the next transition at WDI. Leaving WDI
unconnected disables the watchdog function.
WDI connects to an internal voltage divider
between V
mid-supply when left unconnected. For a simple
check of watchdog function, connect WDI to
either Probe pins GND or V
to go to a Logic Low.
Pin 12 – CE OUT – Chip-Enable Output. The
Chip-Enable (CE) function CE OUT provides
internal gating of chip enable signals to prevent
erroneous data from corrupting the CMOS RAM
in the event of a power failure. During normal
operation, the CE gate is enabled and all CE
transitions are passed from CE IN to CE OUT.
SP691AEB/03
OUT
and GND, which sets it to
OUT
OUT
to cause WDO
to OSC IN,
SP691A/693A Evaluation Board Manual
3
When Reset is asserted, this path is disabled.
Note that CE OUT goes low (active) only when
CE IN is low and V
If CE IN is low when reset is asserted, CE OUT
will stay low for 12 s or until CE IN goes high,
whichever occurs first.
Pin 13 – CE IN – Chip-Enable Input. The Input
to chip-enable gating circuit. Connect to GND
or V
Pin 14 –WDO – Watchdog Output. WDO goes
low and reset is asserted if WDI remains either
high or low longer than the watchdog timeout
period. WDO returns high on the next transition
at WDI. WDO remains high if WDI is
unconnected. WDO is also high when RESET
is asserted.
Pin 15 – RESET – RESET output goes low
whenever V
RESET will remain low for 200ms (when
internal oscillator is used) after V
reset threshold on power-up.
Pin 16 – RESET – RESET Output goes high
whenever V
RESET is open drain and is the inverse of
RESET.
Note: To accurately measure the extremely small
supply current in Battery Back-up mode, you
need to cut split pads SP1 & SP2 (solder side
of board) severing connections to C1 & C2
which would have leakage currents in the
measurement range. Also, remove charging
circuit components CBATT and D1 if they are
installed.
OUT
if not used.
CC
CC
falls below the reset threshold.
falls below the reset threshold.
CC
is above the reset threshold.
© Copyright 2000 Sipex Corporation
CC
crosses the