WM8960CGEFL/RV WOLFSON [Wolfson Microelectronics plc], WM8960CGEFL/RV Datasheet
WM8960CGEFL/RV
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WM8960CGEFL/RV Summary of contents
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Stereo CODEC with 1W Stereo Class D Speaker Drivers and Headphone Drivers for Portable Audio Applications DESCRIPTION The WM8960 is a low power, high quality stereo CODEC designed for portable digital audio applications. Stereo class D speaker drivers provide ...
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WM8960 DESCRIPTION ....................................................................................................... 1 FEATURES ............................................................................................................ 1 APPLICATIONS ..................................................................................................... 1 TABLE OF CONTENTS ......................................................................................... 2 PIN CONFIGURATION .......................................................................................... 3 ORDERING INFORMATION .................................................................................. 3 PIN DESCRIPTION ................................................................................................ 4 ABSOLUTE MAXIMUM RATINGS ........................................................................ 5 RECOMMENDED OPERATING CONDITIONS ..................................................... 5 ELECTRICAL CHARACTERISTICS ..................................................................... ...
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... LINPUT2 3 LINPUT1 4 TOP VIEW RINPUT1 5 RINPUT2 6 RINPUT3/JD3 7 DCVDD ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE WM8960CGEFL/V -40C to +85C WM8960CGEFL/RV -40C to +85C Note: Reel quantity = 3500 SPKGND1 24 SPK_LN 23 SPK_RP 22 SPKVDD2 21 SPKGND2 20 19 SPK_RN SDIN 18 SCLK 17 14 ...
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WM8960 PIN DESCRIPTION PIN NO NAME 1 MICBIAS 2 LINPUT3 / JD2 3 LINPUT2 LINPUT1 4 5 RINPUT1 RINPUT2 6 7 RINPUT3 / JD3 8 DCVDD 9 DGND 10 DBVDD 11 MCLK BCLK 12 DACLRC 13 14 DACDAT 15 ADCLRC ...
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Production Data ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical ...
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WM8960 ELECTRICAL CHARACTERISTICS Test Conditions DCVDD = 1.8V, DBVDD = 3.3V, AVDD = SPKVDD1 = SPKVDD2 = 3.3V, T 24-bit audio data unless otherwise stated. PARAMETER Analogue Inputs (LINPUT1, RINPUT1, LINPUT2, LINPUT3, RINPUT2, RINPUT3) Full-scale Input Signal Level – note ...
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Production Data Test Conditions DCVDD = 1.8V, DBVDD = 3.3V, AVDD = SPKVDD1 = SPKVDD2 = 3.3V, T 24-bit audio data unless otherwise stated. PARAMETER Total Harmonic Distortion Analogue Inputs (LINPUT2, RINPUT2) to ADC out Signal to Noise Ratio (A-weighted) ...
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WM8960 Test Conditions DCVDD = 1.8V, DBVDD = 3.3V, AVDD = SPKVDD1 = SPKVDD2 = 3.3V, T 24-bit audio data unless otherwise stated. PARAMETER Headphone Outputs (HP_L, HP_R) 0dB Full scale output voltage Mute attenuation Channel Separation DAC to Line-Out ...
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Production Data Test Conditions DCVDD = 1.8V, DBVDD = 3.3V, AVDD = SPKVDD1 = SPKVDD2 = 3.3V, T 24-bit audio data unless otherwise stated. PARAMETER Total Harmonic Distortion Plus Noise (LINPUT3 and RINPUT3 to speaker outputs) Signal to Noise Ratio ...
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WM8960 OUTPUT PGA GAIN Output PGA Gains (Target gain, not measured -10 -20 -30 -40 -50 -60 -70 -80 Figure 1 Output PGA Gains (LOUT1VOL, ROUT1VOL, SPKLVOL, SPKRVOL 100 Volume Register Setting ...
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Production Data TYPICAL POWER CONSUMPTION DCVDD (V) Off - Default state at power up 1.71 1.8 1.8 3.6 Off - Thermal sensor disabled, 1.71 no clocks 1.8 1.8 3.6 Sleep - Thermal sensors 1.71 enabled, VMID enabled using 1.8 250k ...
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WM8960 DCVDD (V) Record Mode - Stereo I/P into 1.71 ADC sampling at 16kHz (no 1.8 signal) 1.8 3.6 Record Mode - Stereo I/P into 1.71 ADC sampling at 44.1kHz (no 1.8 signal) 1.8 3.6 Record Mode - Stereo I/P ...
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Production Data SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING MCLK Figure 2 System Clock Timing Requirements Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD1=SPKVDD2=3.3V, DGND=AGND=SPKGND1=SPKGND2=0V, T PARAMETER System Clock Timing Information MCLK cycle time MCLK duty cycle AUDIO INTERFACE TIMING – MASTER MODE Figure 2 ...
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WM8960 Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD1=SPKVDD2=3.3V, DGND=AGND=SPKGND1=SPKGND2=0V, T Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information ADCLRC/DACLRC propagation delay from BCLK falling edge ADCDAT propagation delay from BCLK falling edge DACDAT setup time to BCLK ...
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Production Data CONTROL INTERFACE TIMING – 2-WIRE MODE SDIN SCLK Figure 4 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD1=SPKVDD2=3.3V, DGND=AGND=SPKGND1=SPKGND2=0V, T Mode, fs=48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input ...
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WM8960 INTERNAL POWER ON RESET CIRCUIT Figure 5 Internal Power on Reset Circuit Schematic The WM8960 includes an internal Power-On-Reset Circuit, as shown in Figure 5, which is used to reset the digital logic into a default state after power ...
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Production Data Figure 7 Typical Power up Sequence where DCVDD is Powered before AVDD Figure 7 shows a typical power-up sequence where DCVDD comes up first. First it is assumed that DCVDD is already up to specified operating voltage. When ...
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WM8960 DEVICE DESCRIPTION INTRODUCTION The WM8960 is a low power audio CODEC offering a combination of high quality audio, advanced features, low power and small size. These characteristics make it ideal for portable digital audio applications with stereo speaker and ...
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Production Data INPUT SIGNAL PATH The WM8960 has three flexible stereo analogue input channels which can be configured as line inputs, differential microphone inputs or single-ended microphone inputs. Line inputs and microphone PGA outputs can be routed to the hi-fi ...
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WM8960 Figure 8 Microphone Input PGA Circuit The input PGAs and boost mixers are enabled by the AINL and AINR register bits. The microphone PGAs can be also be disabled independently of the boost mixer to save power, using LMIC ...
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Production Data REGISTER ADDRESS R32 (20h) ADCL Input Signal Path R33 (21h) ADCR Input Signal Path Table 3 Input PGA Control INPUT PGA VOLUME CONTROLS The input PGAs have a gain range from -17.25dB to +30dB in 0.75dB steps. The ...
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WM8960 REGISTER ADDRESS R0 (00h) Left Channel PGA R1 (01h) Right Channel PGA R23 (17h) Additional Control (1) Table 4 Input PGA Volume Control See "Volume Updates" for more information on volume update bits, zero cross and timeout operation. LINE ...
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Production Data INPUT BOOST The input path to the ADCs is via a boost stage, which can mix signals from the microphone PGAs and the line inputs. The boost stage can provide up to +29dB additional gain from the microphone ...
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WM8960 MICROPHONE BIASING CIRCUIT The MICBIAS output provides a low noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network. Refer to the Applications Information section for recommended external components. The MICBIAS voltage can ...
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Production Data EXAMPLE INPUT CONFIGURATIONS Some example input configurations are shown below. Figure 10 Example Microphone Input Configurations (See also "Recommended External Components") w Single-ended MIC configuration on left channel. LINPUT2 and LINPUT3 unused Pseudo-differential MIC configuration on left channel ...
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WM8960 ANALOGUE TO DIGITAL CONVERTER (ADC) The WM8960 uses stereo 24-bit, 64x oversampled sigma-delta ADCs. The use of multi-bit feedback and high oversampling rates reduce the effects of jitter and high frequency noise. The ADC Full Scale input level is ...
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Production Data REGISTER ADDRESS R21 (15h) Left ADC Digital Volume R22 (16h) Right ADC Digital Volume Table 10 ADC Digital Volume Control ADC DIGITAL FILTERS The ADC filters perform true 24-bit signal processing to convert the raw multi-bit oversampled data ...
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WM8960 AUTOMATIC LEVEL CONTROL (ALC) The WM8960 has an automatic level control that aims to keep a constant recording volume irrespective of the input signal level. This is achieved by continuously adjusting the PGA gain so that the signal level ...
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Production Data REGISTER ADDRESS R17 (11h) ALC Control (1) R18 (12h) ALC Control (2) R19 (13h) ALC Control (3) w BIT LABEL DEFAULT 8:7 ALCSEL 00 ALC Function Select [1:0] (OFF ALC off (PGA gain set by register) ...
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WM8960 REGISTER ADDRESS R27 (1Bh) Additional Control (3) Table 12 ALC Control ALC SAMPLE RATE CONTROL The register bits ADC_ALC_SR must be set correctly to ensure that the ALC attack, decay and hold times are correct for the chosen sample ...
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Production Data OUTPUT SIGNAL PATH The hi-fi DACs and DAC digital filters are enabled by register bits DACL and DACR. The mixers and output drivers can be separately enabled by individual control bits (see Analogue Outputs). Thus it is possible ...
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WM8960 REGISTER ADDRESS R10 (0Ah) Left Channel Digital Volume R11 (0Bh) Right Channel Digital Volume Table 15 Digital Volume Control DAC SOFT MUTE AND SOFT UN-MUTE The WM8960 also has a soft mute function, which, when enabled, gradually attenuates the ...
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Production Data REGISTER ADDRESS R5 (05h) ADC and DAC Control (1) R6 (06h) ADC and DAC Control (2) Table 16 DAC Soft-Mute Control DAC DE-EMPHASIS Digital de-emphasis can be applied to the DAC playback data (e.g. when the data comes ...
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WM8960 REGISTER ADDRESS R6 (06h) ADC and DAC Control (2) R23 (17h) Additional Control (1) Table 18 DAC Mono Mix and Phase Invert Select 3D STEREO ENHANCEMENT The WM8960 has a digital 3D enhancement option to artificially increase the separation ...
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Production Data OUTPUT MIXERS Left and right analogue mixers allow the DAC output and analogue bypass paths to be mixed. Programmable attenuation and mute is available on the analogue bypass paths from LINPUT3, RINPUT3 and from the input boost mixers ...
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WM8960 REGISTER ADDRESS R34 (22h) Left Output Mixer Control R45 (2Dh) Bypass (1) R37 (25h) Right Output Mixer Control R46 (2Eh) Bypass (2) Table 22 Left and Right Output Mixer Mute and Volume Control The mono output mixer can output, ...
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Production Data REGISTER ADDRESS R38 (26h) Mono Out Mix (1) R39 (27h) Mono Out Mix (2) R42 (2Ah) Mono Out Volume Table 23 Output Mixer Enable Control When left and right inputs to the mono mixer are both disabled, the ...
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WM8960 REGISTER ADDRESS R2 (02h) LOUT1 Volume R3 (03h) ROUT1 Volume Table 24 LOUT1/ROUT1 Volume Control See "Volume Updates" for more information on volume update bits, zero cross and timeout operation. CLASS D SPEAKER OUTPUTS The SPK_LP/SPK_LN and SPK_RP/SPK_RN output ...
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Production Data REGISTER ADDRESS R40 (28h) Left Speaker Volume R41 (29h) Right Speaker Volume R51 (33h) Class D Control (3) Table 25 SPK_L/SPK_R Volume and Speaker Boost Control To prevent pop noise, DCGAIN and ACGAIN should not be modified while ...
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WM8960 To avoid clipping at speaker supply, SPKVDD1 and SPKVDD2 must be high enough to support the peak output voltage when using DCGAIN and ACGAIN functions. The peak output voltage is AVDD*(DCGAIN+ACGAIN)/2. DCGAIN should normally be set to the same ...
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Production Data ENABLING THE OUTPUTS Each analogue output of the WM8960 can be independently enabled or disabled. The analogue mixer associated with each output is powered on or off along with the output pin. All outputs are disabled by default. ...
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WM8960 When DC blocking capacitors are used, then their capacitance and the load resistance together determine the lower cut-off frequency, f response. Smaller capacitance values will diminish the bass response. Assuming a 32 load and C1 100F: f ...
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Production Data VOLUME UPDATES Volume settings will not be applied to input or output PGAs until a '1' is written to one of the update bits (IPVU, OUT1VU, SPKVU bits). This is to allow left and right channels to be ...
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WM8960 Figure 18 Volume Update using Zero Cross Detection If there is a long period where no zero-crossing occurs, a timeout circuit in the WM8960 will automatically update the volume. The volume updates will occur between one and two timeout ...
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Production Data HEADPHONE JACK DETECT The ADCLRC/GPIO1, LINPUT3/JD2 and RINPUT3/JD3 pins can be selected as headphone jack detect inputs to automatically disable the speaker output and enable the headphone output e.g. when a headphone is plugged into a jack socket. ...
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WM8960 REGISTER ADDRESS R27 (1Bh) Additional Control (3) R48 (30h) Additional Control (4) R23 (17h) Additional Control (1) Table 30 Headphone Jack Detect Figure 20 Example Headset Detection Circuit Using Normally-Open Switch Figure 21 Example Headset Detection Circuit Using Normally-Closed ...
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Production Data REGISTER ADDRESS R23 (17h) Additional Control (1) R48 (30h) Additional Control (4) Table 31 Thermal Shutdown GENERAL PURPOSE INPUT/OUTPUT The WM8960 has three dual purpose input/output pins. The ADCLRC/GPIO1 pin can be configured as a ...
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WM8960 For further details of the Jack detect operation see the Headphone Switch section. DIGITAL AUDIO INTERFACE The digital audio interface is used for inputting DAC data into the WM8960 and outputting ADC data from it. It uses five pins: ...
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Production Data BCLK DIVIDE The BCLK frequency in master mode is controlled by BCLKDIV[3:0]. When the ADCs and DACs are operating at different sample rates, BCLKDIV must be set appropriately to support the data rate of whichever is the faster. ...
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WM8960 Figure DSP/PCM mode, the left channel MSB is available on either the 1 edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data immediately follows left channel data. Depending on word ...
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Production Data Figure 31 DSP/PCM Mode Audio Interface (mode A, LRP=0, Slave) Figure 32 DSP/PCM Mode Audio Interface (mode B, LRP=1, Slave) w WM8960 PD, October 2011, Rev 4.1 51 ...
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WM8960 AUDIO INTERFACE CONTROL The register bits controlling audio format, word length and master / slave mode are summarised in Table 33. MS selects audio interface operation in master or slave mode. In Master mode BCLK, ADCLRC and DACLRC are ...
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Production Data AUDIO INTERFACE OUTPUT TRISTATE Register bit TRIS, register 24(18h) bit[3] can be used to tristate the ADCDAT pin and switch ADCLRC, DACLRC and BCLK to inputs. In Slave mode (MS=0) ADCLRC, DACLRC and BCLK are by default configured ...
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WM8960 REGISTER ADDRESS R24 (18h) Additional Control (2) Table 35 ADCLRC/DACLRC Enable COMPANDING The WM8960 supports A-law and -law companding on both transmit (ADC) and receive (DAC) sides. Companding can be enabled on the DAC or ADC audio interfaces by ...
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Production Data BIT7 SIGN Table 37 8-bit Companded Word Composition Figure 34 µ-Law Companding Figure 35 A-Law Companding w BIT[6:4] EXPONENT u-law Companding 120 100 0.1 0.2 0.3 0.4 Normalised Input A-law Companding 120 ...
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WM8960 LOOPBACK Setting the LOOPBACK register bit enables digital loopback. When this bit is set the output data from the ADC audio interface is fed directly into the DAC data input. The ADCs and DACs must both use DACLRC when ...
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Production Data SYSCLK can either be derived directly from MCLK, or generated from a PLL using MCLK as a reference. The clock source is selected by CLKSEL. Many commonly-used audio sample rates can be derived directly from MCLK, while the ...
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WM8960 REGISTER ADDRESS R8 (08h) Clocking (2) Table 39 ADC, DAC and BCLK Control (=MCLK OR PLL OUTPUT) Table 40 ADC and DAC Sample Rates w BIT LABEL DEFAULT 8:6 DCLKDIV 3:0 BCLKDIV[3:0] 0000 SYSCLK ADCDIV OR DACDIV (MHz) 000 ...
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Production Data Although the ADC and DAC can run at different sample rates, they share the same bit clock pin BCLK. When operating in master mode, register bits BCLKDIV[3:0] should be set to an appropriate value to ensure that there ...
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WM8960 DEEMPH, 3DUC and 3DUC should be configured to match the chosen DAC sample rate. REGISTER ADDRESS R27 (1Bh) Additional Control (3) R5 (05h) ADC and DAC Control (1) R16 (10h) 3D Enhance Table 42 Additional Sample Rate Controls PLL ...
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Production Data REGISTER ADDRESS R52 (34h) PLL N value R53 (35h) PLL K value (1) R54 (36h) PLL K Value (2) R55 (37h) PLL K Value (3) Table 44 PLL Frequency Ratio Control The PLL performs best when f example ...
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WM8960 Table 46 Example Clocking Schemes w Device running in master mode with 24-bit data MCLK input at 12.288MHz ADC and DAC running at fs=48kHz BCLK running at 64fs Device running in slave mode with 24-bit data MCLK input at ...
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Production Data CONTROL INTERFACE 2-WIRE SERIAL CONTROL INTERFACE The WM8960 is controlled by writing to registers through a 2-wire serial control interface. A control word consists of 16 bits. The first 7 bits (B15 to B9) are address bits that ...
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WM8960 REGISTER ADDRESS R25 (19h) Power Management (1) w BIT LABEL DEFAULT 8:7 VMIDSEL 00 Vmid Divider Enable and Select 00 = Vmid disabled (for OFF mode 50k divider enabled (for playback / record ...
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Production Data REGISTER ADDRESS R26 (1Ah) Power Management (2) R47 (2Fh) Power Management (3) Table 47 Power Management w BIT LABEL DEFAULT 8 DACL 0 DAC Left 0 = Power down 1 = Power up 7 DACR 0 DAC Right ...
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WM8960 STOPPING THE MASTER CLOCK In order to minimise power consumed in the digital core of the WM8960, the master clock may be stopped in Standby and OFF modes. If this cannot be done externally at the clock source, the ...
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Production Data REGISTER MAP REGISTER remarks Bit[8] R0 (00h) Left Input volume IPVU R1 (01h) Right Input volume IPVU R2 (02h) LOUT1 volume OUT1VU R3 (03h) ROUT1 volume OUT1VU R4 (04h) Clocking (1) R5 (05h) ADC & DAC Control (CTR1) ...
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WM8960 REGISTER BITS BY ADDRESS REGISTER BIT LABEL ADDRESS R0 (00h) 8 IPVU Left Input Volume 7 LINMUTE 6 LIZC 5:0 LINVOL[5:0] R1 (01h) 8 IPVU Right Input Volume 7 RINMUTE 6 RIZC 5:0 RINVOL[5:0] R2 (02h) 8 OUT1VU LOUT1 ...
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Production Data REGISTER BIT LABEL ADDRESS 6:0 ROUT1VOL[6:0] R4 (04h) 8:6 ADCDIV[2:0] Clocking (1) 5:3 DACDIV[2:0] 2:1 SYSCLKDIV[1:0] 0 CLKSEL R5 (05h) 8 ADC and 7 DACDIV2 DAC Control (1) 6:5 ADCPOL[1: DACMU 2:1 DEEMPH[1:0] w DEFAULT DESCRIPTION ...
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WM8960 REGISTER BIT LABEL ADDRESS 0 ADCHPD R6 (06h) 8:7 ADC and 6:5 DACPOL[1:0] DAC Control ( DACSMM 2 DACMR 1 DACSLOPE 0 R7 (07h) 8 ALRSWAP Audio Interface 7 BCLKINV DLRSWAP 4 LRP 3:2 ...
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Production Data REGISTER BIT LABEL ADDRESS 1:0 FORMAT[1:0] R8 (08h) 8:6 DCLKDIV[2:0] Clocking (2) 5:4 3:0 BCLKDIV[3:0] R9 (09h) 8:7 Audio 6 ALRCGPIO Interface 5 WL8 4:3 DACCOMP[1:0] 2:1 ADCCOMP[1:0] 0 LOOPBACK w DEFAULT DESCRIPTION Right justified ...
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WM8960 REGISTER BIT LABEL ADDRESS R10 (0Ah) 8 DACVU Left DAC Volume 7:0 LDACVOL[7:0] R11 (0Bh) 8 DACVU Right DAC Volume 7:0 RDACVOL[7:0] R12 (0Ch) 8:0 R13 (0Dh) 8:0 R14 (0Eh) 8:0 R15 (0Fh) 8:0 Reset Reset R16 {10h) 8 ...
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Production Data REGISTER BIT LABEL ADDRESS 6:4 MAXGAIN[2:0] 3:0 ALCL[3:0] R18 (12h) 8 ALC (2) 7 6:4 MINGAIN[2:0] 3:0 HLD[3:0] R19 (13h) 8 ALCMODE ALC (3) 7:4 DCY[3:0] 3:0 ATK[3:0] R20 (14h) 8 Noise 7:3 NGTH[4:0] Gate w DEFAULT DESCRIPTION ...
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WM8960 REGISTER BIT LABEL ADDRESS 2:1 0 NGAT R21 (15h) 8 ADCVU Left ADC Volume 7:0 LADCVOL[7:0] R22 (16h) 8 ADCVU Right ADC Volume 7:0 RADCVOL[7:0] R23 (17h) 8 TSDEN Additional Control (1) 7:6 VSEL[1: DMONOMIX 3:2 DATSEL[1:0] ...
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Production Data REGISTER BIT LABEL ADDRESS Additional 6 HPSWEN Control (2) 5 HPSWPOL 4 3 TRIS 2 LRCM 1:0 R25 (19h) 8:7 VMIDSEL[1:0] Power Mgmt (1) 6 VREF 5 AINL 4 AINR 3 ADCL 2 ADCR 1 MICB 0 DIGENB ...
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WM8960 REGISTER BIT LABEL ADDRESS 7 DACR 6 LOUT1 5 ROUT1 4 SPKL 3 SPKR 2 1 OUT3 0 PLL_EN R27 (1Bh) 8:7 Additional 6 VROI Control ( OUT3CAP 2:0 ADC_ALC_SR R28 (1Ch) 8 Anti-Pop 1 7 ...
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Production Data REGISTER BIT LABEL ADDRESS 3 BUFIOEN 2 SOFT_ST 1 0 HPSTBY R29 (1Dh) 8:7 Anti-pop 2 6 DISOP 5:4 DRES[1:0] 3:0 R30 (1Eh) 8:0 R31 (1Fh) 8:0 R32 (20h) 8 LMN1 ADCL Signal Path 7 LMP3 6 LMP2 ...
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WM8960 REGISTER BIT LABEL ADDRESS 7 RMP3 6 RMP2 5:4 RMICBOOST[1:0] 3 RMIC2B 2:0 R34 (22h) 8 LD2LO Left Out Mix 7 LI2LO 6:4 LI2LOVOL[2:0] 3:0 R35 (23h) 8:0 R36 (24h) 8:0 R37 (25h) 8 RD2RO Right Out Mix 7 ...
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Production Data REGISTER BIT LABEL ADDRESS R40 (28h) 8 SPKVU Left Speaker Volume 7 SPKLZC 6:0 SPKLVOL[6:0] R41 (29h) 8 SPKVU Right Speaker Volume 7 SPKRZC 6:0 SPKRVOL[6:0] R42 (2Ah) 8:7 OUT3 6 MOUTVOL Volume 5:0 R43 (2Bh) 8:7 Left ...
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WM8960 REGISTER BIT LABEL ADDRESS Left 7 LB2LO Bypass 6:4 LB2LOVOL[2:0] 3:0 R46 (2Eh) 8 Right 7 RB2RO Bypass 6:4 RB2ROVOL[2:0] 3:0 R47 (2Fh) 8:6 Power 5 LMIC Mgmt (3) 4 RMIC 3 LOMIX 2 ROMIX 1:0 R48 (30h) 8 ...
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Production Data REGISTER BIT LABEL ADDRESS 0 MBSEL R49 (31h) 8 Class D 7:6 SPK_OP_EN[1:0] Control (1) 5:0 R50 (32h) 8:0 R51 (33h) 8:6 Class D 5:3 DCGAIN[2:0] Control (2) 2:0 ACGAIN[2:0] R52 (34h) 8:6 OPCLKDIV[2:0] PLL (1) 5 SDM ...
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WM8960 REGISTER BIT LABEL ADDRESS R55 (37h) 8 PLL (4) 7:0 PLLK[7:0] DIGITAL FILTER CHARACTERISTICS PARAMETER ADC Filter Passband Passband Ripple Stopband Stopband Attenuation DAC Normal Filter Passband Passband Ripple Stopband Stopband Attenuation DAC Sloping Stopband Filter Passband Passband Ripple ...
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Production Data ADC FILTER RESPONSES 10 -10 -30 -50 -70 -90 -110 -130 -150 Frequency (fs) Figure 38 ADC Digital Filter Frequency Response DAC FILTER RESPONSES DAC STOPBAND ATTENUATION The DAC digital filter type is selected by the DACSLOPE register ...
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WM8960 MAGNITUDE(dB) 10 -10 0 0.5 1 1.5 -30 -50 -70 -90 -110 -130 -150 Frequency (fs) Figure 42 DAC Digital Filter Frequency Response (Sloping Stopband Mode 0.05 -0.05 -0.1 -0.15 -0.2 -0.25 ...
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Production Data DE-EMPHASIS FILTER RESPONSES MAGNITUDE(dB 5000 10000 - -10 Frequency (Hz) Figure 44 De-Emphasis Digital Filter Response (32kHz) MAGNITUDE(dB 5000 10000 15000 - ...
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WM8960 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS SPEAKER SELECTION For filterless operation important to select a speaker with appropriate internal inductance. The internal inductance and the speaker's load resistance create a low-pass filter with a cut-off frequency of: e.g. ...
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Production Data Figure 50 Speaker Equivalent Circuit PCB LAYOUT CONSIDERATIONS The efficiency of the speaker drivers is affected by the series resistance between the WM8960 and the speaker (e.g. inductor ESR) as shown in Figure 51. This resistance should be ...
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WM8960 Figure 52 EMI Reduction Techniques w Production Data PD, October 2011, Rev 4.1 88 ...
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Production Data PACKAGE DIMENSIONS FL: 32 PIN QFN PLASTIC PACKAGE EXPOSED 6 GROUND PADDLE BOTTOM VIEW A3 C SIDE VIEW SEATING PLANE M W Exposed lead ...
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... Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner. Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. ...
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... Production Data REVISION HISTORY DATE REV ORIGINATOR 23/09/11 4.1 JMacD 23/09/11 4.1 JMacD w CHANGES Order codes changed from WM8960GEFL/V and WM8960GEFL/RV to WM8960CGEFL/V and WM8960CGEFL/RV to reflect change to copper wire bonding. Package Diagram changed to DM101.A. WM8960 PD, October 2011, Rev 4.1 91 ...