WM8973_05 WOLFSON [Wolfson Microelectronics plc], WM8973_05 Datasheet - Page 13

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WM8973_05

Manufacturer Part Number
WM8973_05
Description
Stereo CODEC for Portable Audio Applications
Manufacturer
WOLFSON [Wolfson Microelectronics plc]
Datasheet
Production Data
w
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
AUDIO INTERFACE TIMING – MASTER MODE
Test Conditions
CLKDIV2=0, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, T
unless otherwise stated.
PARAMETER
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
MCLK duty cycle
Test Conditions
CLKDIV2=1, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, T
unless otherwise stated.
PARAMETER
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
Figure 1 System Clock Timing Requirements
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)
MCLK
ADCLRC/
(Outputs)
DACLRC
ADCDAT
DACDAT
(Output)
BCLK
SYMBOL
SYMBOL
T
T
T
T
T
T
T
MCLKDS
MCLKH
MCLKH
MCLKL
MCLKY
MCLKL
MCLKY
A
A
t
MCLKL
= +25
= +25
t
MCLKY
o
o
t
t
C, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data,
C, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data,
DST
MCLKH
t
DHT
60:40
MIN
MIN
21
21
54
10
10
27
TYP
TYP
t
DL
t
DDA
PD Rev 4.2 September 2005
40:60
MAX
MAX
WM8973L
UNIT
UNIT
ns
ns
ns
ns
ns
ns
13

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