WM8772EFT WOLFSON [Wolfson Microelectronics plc], WM8772EFT Datasheet
WM8772EFT
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WM8772EFT Summary of contents
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Codec with Volume Control DESCRIPTION The WM8772 is a multi-channel audio codec ideal for DVD and surround sound processing applications for home hi-fi, automotive and other audio visual equipment. A stereo 24-bit multi-bit sigma delta ADC ...
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... AUDIO INTERFACE STEREO & DAC DIGITAL FILTERS STEREO DAC W CONTROL INTERFACE Production Data VOUT1L LOW PASS FILTER VOUT1R VOUT2L LOW PASS FILTER VOUT2R VOUT3L LOW PASS FILTER VOUT3R WM8772EFT * extra pins on TQFP allow separate clocking of ADC and DAC PD Rev 4.1 October 2004 2 ...
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Production Data DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM - 28 PIN SSOP ........................................................................1 BLOCK DIAGRAM – 32 PIN TQFP........................................................................2 TABLE OF CONTENTS .........................................................................................3 PIN CONFIGURATION - 28 LEAD SSOP .............................................................5 ORDERING INFORMATION ..................................................................................5 PIN CONFIGURATION 32 LEAD TQFP...............................................................6 ORDERING ...
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WM8772 APPLICATIONS INFORMATION .........................................................................66 RECOMMENDED EXTERNAL COMPONENTS .......................................................... 66 SUGGESTED ANALOGUE LOW PASS POST DAC FILTERS...........................67 PACKAGE DIMENSIONS ....................................................................................69 IMPORTANT NOTICE ..........................................................................................70 ADDRESS: .................................................................................................................. 70 w Production Data PD Rev 4.1 October 2004 4 ...
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Production Data PIN CONFIGURATION - 28 LEAD SSOP MODE 1 MCLK 2 BCLK 3 LRC 4 DVDD 5 DGND 6 DIN1 7 DIN2 8 DIN3 9 DOUT 10 ML/I2S 11 MC/IWL 12 MD/DM 13 MUTE 14 ORDERING INFORMATION TEMPERATURE DEVICE ...
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... AVDD MODE ADCMCLK DACMLCK ADCBCLK DACBCLK ORDERING INFORMATION TEMPERATURE DEVICE RANGE o WM8772EFT - WM8772SEFT/V - WM8772EFT/R - WM8772SEFT/RV -25 to +85 C Note: Reel quantity = 2,200 w DACVREFP DACVREFN ADCVREFN REFADC MUTE MD/DM MC/IWL ML/I2S MOISTURE SENSITIVITY PACKAGE ...
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Production Data PIN DESCRIPTION – 28 LEAD SSOP PIN NAME 1 MODE Digital input 2 MCLK Digital input 3 BCLK Digital input/output 4 LRC Digital input/output 5 DVDD 6 DGND 7 DIN1 Digital input 8 DIN2 Digital input 9 DIN3 ...
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WM8772 PIN DESCRIPTION – 32 LEAD TQFP PIN NAME 1 ADCLRC Digital Input/Output 2 DACLRC Digital Input/Output 3 DVDD 4 DGND 5 DIN1 6 DIN2 7 DIN3 8 DOUT Digital Output 9 ML/I2S 10 MC/IWL 11 MD/DM 12 MUTE Digital ...
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Production Data ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical ...
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WM8772 RECOMMENDED OPERATING CONDITIONS PARAMETER Digital supply range Analogue supply range AVDD, VREFP Ground AGND, VREFN, DGND Difference DGND to AGND Note: Digital supply DVDD must never be more than 0.3V greater than AVDD. ELECTRICAL CHARACTERISTICS Test Conditions AVDD, VREFP ...
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Production Data Test Conditions AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, DGND = 0V, T version unless otherwise stated. ADC/DAC in Slave Mode unless otherwise stated. PARAMETER ADC Performance Input Signal Level (0dB) Input resistance Input ...
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WM8772 TERMINOLOGY 1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). 2. ...
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Production Data DIGITAL FILTER CHARACTERISTICS PARAMETER Passband Passband ripple Stopband Stopband Attenuation Passband Passband ripple Stopband Stopband Attenuation Table 1 Digital Filter Characteristics DAC FILTER RESPONSES 0 -20 -40 -60 -80 -100 -120 0 0.5 1 1.5 Frequency (Fs) Figure ...
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WM8772 ADC FILTER RESPONSES 0 -20 -40 -60 -80 0 0.5 1 1.5 Frequency (Fs) Figure 5 ADC Digital Filter Frequency Response ADC HIGH PASS FILTER The WM8772EDS has a selectable digital high pass filter to remove DC offsets. The ...
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Production Data - Frequency (kHz) Figure 9 De-Emphasis Frequency Response (44.1KHz - Frequency (kHz) Figure 11 De-Emphasis Frequency Response (48kHz) w 0.4 0.3 0.2 ...
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... WM8772EDS – 28 PIN SSOP PAGES DESCRIBE THE OPERATION OF THE WM8772EDS 28 PIN SSOP PRODUCT VARIANT. PAGES DESCRIBE THE OPERATION OF THE WM8772EFT 32 PIN TQFP PRODUCT VARIANT. WM8772EDS – 28 PIN SSOP MASTER CLOCK TIMING MCLK Figure 13 ADC and DAC Master Clock Timing Requirements Test Conditions AVDD, VREFP = 5V, DVDD = 3 ...
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Production Data BCLK (Output) LRC (Output) DOUT DIN1/2/3 Figure 15 Digital Audio Data Timing – Master Mode Test Conditions AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN, DGND = 0V, T otherwise stated. PARAMETER SYMBOL Audio Data Input Timing ...
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WM8772EDS – 28 PIN SSOP DIGITAL AUDIO INTERFACE – SLAVE MODE LRC BCLK WM8772 CODEC DOUT DIN1/2/3 Figure 16 Audio Interface – Slave Mode BCLK LRC DIN1/2/3 DOUT Figure 17 Digital Audio Data Timing – Slave Mode Test Conditions AVDD ...
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Production Data Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, T stated. PARAMETER SYMBOL DOUT propagation delay t DD from BCLK falling edge Table 4 Digital Audio Data Timing – Slave Mode MPU INTERFACE ...
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WM8772EDS – 28 PIN SSOP DEVICE DESCRIPTION INTRODUCTION WM8772EDS is a complete 6-channel DAC, 2-channel ADC audio codec, including digital interpolation and decimation filters, multi-bit sigma delta stereo ADC, and switched capacitor multi- bit sigma delta DACs with digital volume ...
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Production Data SAMPLING RATE (LRC) 32kHz 44.1kHz 48kHz 96kHz 192kHz Table 6 System Clock Frequencies Versus Sampling Rate HARDWARE CONTROL MODES When the MODE pin is held high, the following hardware modes of operation are available. Note: When in hardware ...
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WM8772EDS – 28 PIN SSOP The MUTE pin is an input to select mute or not mute. MUTE is active high; taking the pin high causes the filters to soft mute, ramping down the audio signal over a few milliseconds. ...
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Production Data DIGITAL AUDIO INTERFACE MASTER AND SLAVE MODES The audio interface operates in either Slave or Master mode, selectable using the MS control bit. In both Master and Slave modes DIN1/2/3 are always inputs to the WM8772EDS and DOUT ...
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WM8772EDS – 28 PIN SSOP AUDIO INTERFACE FORMATS Audio data is applied to the internal DAC filters, or output from the ADC filters, via the Digital Audio Interface. 5 popular interface formats are supported: Left Justified mode Right Justified mode ...
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Production Data RIGHT JUSTIFIED MODE In right justified mode, the LSB of DIN1/2/3 is sampled by the WM8772EDS on the rising edge of BCLK preceding a LRC transition. The LSB of the ADC data is output on DOUT and changes ...
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WM8772EDS – 28 PIN SSOP The MSB of the left channel ADC data is output on DOUT and changes on the first falling edge of BCLK following a low to high LRC transition and may be sampled on the rising ...
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Production Data In both early and late DSP modes, DACL1 is always sent first, followed immediately by DACR1 and the data words for the other 6 channels. No BCLK edges are allowed between the data words. The word order is ...
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WM8772EDS – 28 PIN SSOP REGISTER MAP - 28 PIN SSOP The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8772EDS can be configured using the Control ...
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Production Data CONTROL INTERFACE REGISTERS ATTENUATOR CONTROL MODE Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and right channel DACs from the next audio input sample. No update to the attenuation ...
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WM8772EDS – 28 PIN SSOP ADC AND DAC DIGITAL AUDIO INTERFACE CONTROL REGISTER Interface format is selected via the FMT[1:0] register bits: REGISTER ADDRESS Interface Control In left justified, right justified set high, the expected polarity of ...
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Production Data DAC OUTPUT PHASE The DAC Phase control word determines whether the output of each DAC is non-inverted or inverted REGISTER ADDRESS DAC Phase DIGITAL ZERO CROSS-DETECT The Digital volume control also incorporates a zero cross detect circuit which ...
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WM8772EDS – 28 PIN SSOP Setting the MUTEALL register bit will apply a 'soft' mute to the input of all the DAC digital filters: REGISTER ADDRESS Refer to Figure 19 for the plot of application and release of soft mute. ...
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Production Data POWERDOWN MODE AND ADC/DAC DISABLE Setting the PDWN register bit immediately powers down the DAC’s on the WM8772EDS, overriding the DACD powerdown bits control bits. All trace of the previous input samples are removed, but all control register ...
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WM8772EDS – 28 PIN SSOP MASTER MODE LRC FREQUENCY SELECT In Master mode the WM8772EDS generates LRC and BCLK. These clocks are derived from the master clock and the ratio of MCLK to LRC is set by RATE. REGISTER ADDRESS ...
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Production Data DAC DIGITAL VOLUME CONTROL The DAC volume may also be adjusted in the digital domain using independent digital attenuation control registers REGISTER BIT LABEL ADDRESS 7:0 0000000 LDA1[7:0] Digital Attenuation 8 UPDATE DACL1 0000001 7:0 RDA1[6:0] Digital Attenuation ...
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WM8772EDS – 28 PIN SSOP SOFTWARE REGISTER RESET Writing to register 11111 will cause a register reset, resetting all register bits to their default values. The device will be held in this reset state until a subsequent register write to ...
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Production Data APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS RECOMMENDED EXTERNAL COMPONENTS VALUES COMPONENT SUGGESTED REFERENCE VALUE C1 and 0 and and C10 0 and C11 10 F ...
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WM8772EDS – 28 PIN SSOP SUGGESTED ANALOGUE LOW PASS POST DAC FILTERS It is recommended that a lowpass filter be applied to the output from each DAC channel for Hi Fi applications. Typically a second order filter is suitable and ...
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Production Data To ensure that system ‘pop’ noise is kept to a minimum when power is applied or removed, a transistor clamp circuit arrangement may be added to the output connectors of the system. A recommended clamp circuit configuration is ...
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WM8772EDS – 28 PIN SSOP PACKAGE DIMENSIONS DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm Dimensions Symbols (mm) MIN NOM A ----- A 0. 1.65 1. 0.22 c ...
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... CODEC DOUT DIN1/2/3 3 Figure 34 Audio Interface - Master Mode w t MCLKL t MCLKH t MCLKY SYMBOL TEST CONDITIONS t MCLKH t MCLKL t MCLKY DSP/ ENCODER/ DECODER WM8772EFT – 32 PIN TQFP 48kHz, DACMCLK and A MIN TYP MAX 40:60 60:40 PD Rev 4.1 October 2004 UNIT ...
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... WM8772EFT – 32 PIN TQFP ADCBCLK/ DACBCLK (Outputs) ADCLRC/ DACLRC (Outputs) DOUT DIN1/2/3 Figure 35 Digital Audio Data Timing – Master Mode Test Conditions AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN, DGND = 0V, T ADCMCLK = 256fs unless otherwise stated. PARAMETER SYMBOL Audio Data Input Timing Information ...
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... DACLRC DOUT DIN1/2/3 3 Figure 36 Audio Interface – Slave Mode t BCH DACBCLK/ ADCBCLK DACLRC/ ADCLRC DIN1/2/3 DOUT Figure 37 Digital Audio Data Timing – Slave Mode w DSP ENCODER/ DECODER t BCL t BCY LRSU DS LRH WM8772EFT – 32 PIN TQFP PD Rev 4.1 October 2004 43 ...
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... WM8772EFT – 32 PIN TQFP Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, T unless otherwise stated. PARAMETER SYMBOL Audio Data Input Timing Information ADCBCLK/DACBCLK cycle t BCY time ADCBCLK/DACBCLK pulse t BCH width high ADCBCLK/DACBCLK pulse t BCL width low ADCLRC/DACLRC set-up t LRSU time to ADCBCLK/DACBCLK rising ...
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... MD/DM to MC/IWL set-up time MC/IWL to MD/DM hold time ML/I2S pulse width low ML/I2S pulse width high ML/I2S rising to MC/IWL rising Table 16 3-Wire SPI Compatible Control Interface Input Timing Information w WM8772EFT – 32 PIN TQFP 48kHz, DACMCLK and ADCMCLK = 256fs unless otherwise A SYMBOL MIN ...
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... ADC and DAC. The DAC master clock for WM8772EFT supports audio sampling rates from 128fs to 768fs, where fs is the audio sampling frequency (DACLRC) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz (for DAC operation only) ...
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... Production Data The signal processing for the WM8772EFT typically operates at an oversampling rate of 128fs for both ADC and DAC. The exception to this for the DAC is for operation with a 128/192fs system clock, e.g. for 192kHz operation, when the oversampling rate is 64fs. For ADC operation at 96kHz it is recommended that the user set the ADCOSR bit ...
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... WM8772EFT – 32 PIN TQFP 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 Figure 39 Application and Release of Soft Mute The MUTE pin is an input to select mute or not mute. MUTE is active high; taking the pin high causes the filters to soft mute, ramping down the audio signal over a few milliseconds. Taking MUTE low again allows data into the filter ...
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... The audio interface operates in either Slave or Master mode, selectable using the DACMS and ADCMS control bits. In both Master and Slave modes DIN1/2/3 are always inputs to the WM8772EFT and DOUT is always an output. The default is Slave mode for ADC and DAC. In Slave mode, ADCLRC, DACLRC and ADCBCLK, DACBCLK are inputs to the WM8772EFT (Figure 21) ...
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... WM8772EFT – 32 PIN TQFP DIN1/2/3 are sampled by the WM8772EFT on the rising edge of DACBCLK so the controller must output DAC data that changes on the falling edge of DACBCLK. ADC data is output on DOUT and changes on the falling edge of ADCBCLK. By setting control bit DACBCP the polarity of DACBCLK may be reversed so that DIN1/2/3 are sampled on the falling edge of DACBCLK ...
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... Production Data LEFT JUSTIFIED MODE In left justified mode, the MSB of DIN1/2/3 is sampled by the WM8772EFT on the first rising edge of DACBCLK following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on the same falling edge of ADCBCLK as ADCLRC and may be sampled on the rising edge of ADCBCLK ...
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... Figure 45 I DSP EARLY MODE In DSP early mode, the MSB of DAC channel 1 left data is sampled by the WM8772EFT on the second rising edge on DACBCLK following a DACLRC rising edge. DAC channel 1 right and DAC channels 2 and 3 data follow DAC channel 1 left data (Figure 46). ...
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... Figure 47 DSP Early Mode Timing Diagram – ADC Data Output DSP LATE MODE In DSP late mode, the MSB of DAC channel 1 left data is sampled by the WM8772EFT on the first DACBCLK rising edge following a DACLRC rising edge. DAC channel 1 right and DAC channels 2 and 3 data follow DAC channel 1 left data (Figure 48). ...
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... DZFM[1:0] Table 21 Zero Flag Output Select SOFTWARE CONTROL INTERFACE OPERATION The WM8772EFT is controlled using a 3-wire serial interface in software mode or pin programmable in hardware mode. The control mode is selected by the state of the MODE pin. The control interfaces are 5V tolerant; meaning that the control interface input signals ML/I2S, MC/IWL and MD/DM may have an input high level of 5V while DVDD is 3V ...
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... Production Data REGISTER MAP – 32 PIN TQFP The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8772EFT can be configured using the Control Interface. All unused bits should be set to ‘0’. REGISTER B15 B14 ...
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... WM8772EFT – 32 PIN TQFP CONTROL INTERFACE REGISTERS ATTENUATOR CONTROL MODE Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and right channel DACs from the next audio input sample. No update to the attenuation registers is required for ATC to take effect. ...
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... Note: If 32-bit mode is selected in right justified mode, the WM8772EFT defaults to 24 bits. In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the DAC is programmed to receive bit data, the WM8772EFT pads the unused LSBs with zeros. If the DAC is programmed into 32 bit mode, the 8 LSBs are ignored. ...
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... MUTEB pin. A ‘1’ on MUTE indicates 1024 consecutive zero input samples to the DAC channels selected. REGISTER ADDRESS DAC MUTE MODES The WM8772EFT has individual mutes for each of the three DAC channels. Setting MUTE for a channel will apply a ‘soft’ mute to the input of the digital filters of the channel muted. REGISTER ADDRESS DMUTE [2:0] ...
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... DE-EMPHASIS 100 Not DE-EMPHASIS 101 DE-EMPHASIS 110 Not DE-EMPHASIS BIT LABEL 0000010 1 DEEMP ALL WM8772EFT – 32 PIN TQFP DEFAULT DESCRIPTION Soft Mute Select Normal operation 1: Soft mute all channels DEFAULT DESCRIPTION 0 ADC Mute Select Normal operation 1: mute ADC right 0 ...
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... Interface Control DAC MASTER MODE SELECT Control bit DACMS selects between audio interface Master and Slave Modes. In Master mode DACLRC and DACBCLK are outputs and are generated by the WM8772EFT. In Slave mode DACCLRC, DACLRC and DACBCLK are inputs to WM8772EFT. REGISTER ADDRESS Interface Control ...
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... In all modes, the data is signed 2's complement. ADC MASTER MODE SELECT Control bit ADCMS selects between audio interface Master and Slave Modes. In Master mode ADCLRC and ADCBCLK are outputs and are generated by the WM8772EFT. In Slave mode ADCLRC and ADCBCLK are inputs to WM8772EFT. REGISTER ADDRESS ...
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... WM8772EFT – 32 PIN TQFP MASTER MODE ADCLRC FREQUENCY SELECT In Master mode the WM8772EFT generates ADCLRC and ADCBCLK. These clocks are derived from the master clock and the ratio of ADCMCLK to ADCLRC is set by ADCRATE. REGISTER ADDRESS ADCLRC and ADCBCLK Frequency Select ADC OVERSAMPLING RATE SELECT For ADC operation at 96kHz it is recommended that the user set the ADCOSR bit ...
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... ADCBCP BIT LABEL 0001100 6 MPD BIT LABEL 0001100 7 SYNC WM8772EFT – 32 PIN TQFP DEFAULT DESCRIPTION 0 ADCBCLK Polarity (DSP Modes): 0: normal BCLK polarity 1: inverted BCLK polarity DEFAULT DESCRIPTION 0 MUTE Pin Decode Disable: 0: MUTE pin decode enable 1: MUTE pin decode disable DEFAULT ...
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... WM8772EFT – 32 PIN TQFP DAC DIGITAL VOLUME CONTROL The DAC volume may also be adjusted in the digital domain using independent digital attenuation control registers REGISTER BIT LABEL ADDRESS 0000000 7:0 LDA1[7:0] Digital Attenuation 8 UPDATE DACL1 0000001 7:0 RDA1[6:0] Digital Attenuation 8 UPDATE DACR1 7:0 0000100 LDA2[7:0] ...
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... Production Data SOFTWARE REGISTER RESET Writing to register 11111 will cause a register reset, resetting all register bits to their default values. The device will be held in this reset state until a subsequent register write to any address is completed. w WM8772EFT – 32 PIN TQFP PD Rev 4.1 October 2004 65 ...
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... WM8772EFT – 32 PIN TQFP APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS RECOMMENDED EXTERNAL COMPONENTS VALUES COMPONENT SUGGESTED REFERENCE VALUE C1 and 0 and and C10 0 and C11 10 F C12 330 Table 23 External Components Description w DESCRIPTION De-coupling for DVDD and AVDD. ...
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... DAC structure used in WM8772EFT produces much less high frequency output noise than normal sigma delta DACs. This filter is typically also used to provide the 2x gain needed to provide the standard 2Vrms output level from most consumer equipment ...
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... WM8772EFT – 32 PIN TQFP To ensure that system ‘pop’ noise is kept to a minimum when power is applied or removed, a transistor clamp circuit arrangement may be added to the output connectors of the system. A recommended clamp circuit configuration is shown below. Figure 52 Output Clamp Circuit When the +VS power supply is applied, PNP transistor Q10 of the trigger circuit is held on until capacitor C49 is fully charged. With transistor Q10 held ‘ ...
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... B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MS-026, VARIATION = ABA. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS -C- SEATING PLANE ccc C MAX 1.20 0.15 1.05 0.45 0.20 0. WM8772EFT – 32 PIN TQFP DM028 Rev 4.1 October 2004 69 ...
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... WM8772EFT – 32 PIN TQFP IMPORTANT NOTICE Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability ...