ISPPAC-CLK5610V-01T100C LATTICE [Lattice Semiconductor], ISPPAC-CLK5610V-01T100C Datasheet - Page 42
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ISPPAC-CLK5610V-01T100C
Manufacturer Part Number
ISPPAC-CLK5610V-01T100C
Description
In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
Manufacturer
LATTICE [Lattice Semiconductor]
Datasheet
1.ISPPAC-CLK5610V-01T100C.pdf
(47 pages)
- Current page: 42 of 47
- Download datasheet (863Kb)
Lattice Semiconductor
ispClock5600 Family Data Sheet
GOE – Global output enable. This pin drives all outputs to a high-impedance state when it is pulled HIGH. GOE
also controls the internal feedback buffer, so that bringing GOE high will cause the PLL to lose lock.
PS0, PS1 – These input pins are used to select one of four user-defined configuration profiles for the device.
PLL_BYPASS – When this pin is pulled LOW, the V-dividers are driven from the output of the device’s VCO, and
the device behaves as a phase-locked loop. When this pin is pulled HIGH, the V-dividers are driven directly from
the output of the M-divider, and the PLL functions are effectively bypassed.
RESET – When this pin is pulled HIGH, all on-board counters are reset, and lock is lost.
TEST1,TEST2 – These pins are used for factory test functions, and should always be tied to ground.
n/c – These pins have no internal connection. We recommend that they be left unconnected.
RESERVED – These pins are reserved for factory use and should be left unconnected.
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