TCS3104 TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], TCS3104 Datasheet - Page 6

• Manufacturer Part Number: TCS3104
• Description: LIGHT-TO-VOLTAGE COLOR SENSOR
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

TCS3103, TCS3104
LIGHT-TO-VOLTAGE COLOR SENSOR
TAOS108B − JULY 2010
Power Supply Considerations
Output Interface
Device Power Up
PCB Pad Layout
NOTES: A. All linear dimensions are in millimeters.
6
Copyright E 2010, TAOS Inc.
The power supply lines (V
short leads (ideally, a surface mount ceramic type) as close as possible to the device package.
Although the output of the device can be connected to a comparator for simple threshold measurements, or to
another amplifier stage, most applications will require that the three channels be connected to analog-to-digital
converters (ADCs) so that the light and color information can be processed by a microcontroller, computer, or
other device. In many cases, the outputs can be directly connected to the ADC inputs. In some cases, for
example if the light is modulated, it may be desirable to insert active or passive low-pass filters on the channels
prior to the ADC, to smooth out the modulation ripple that would otherwise result in noisy measurements. The
cutoff frequency of the filters would, of course, depend upon the modulation frequency of the incoming light. With
a pulse-width modulated (PWM) input light signal, it may be possible to synchronize the ADC sampling with the
on-time of the PWM signal. In this case, a low-pass filter would not be required because the device output would
be sampled only during the on time of the input light source. A recommendation for minimum pulse width
would be 3
The TCS310x should use the following power up sequence: A stable ground reference from the system should
be applied first, followed by the V
pin is floating or without a ground reference. Afterward, the MFP pin may be biased or driven. The MFP pin must
always have a valid logic reference level. The pin may be biased or driven to a logical high or logical low level.
Suggested PCB pad layout guidelines for the Dual Flat No-Lead (FN) surface mount package are shown in
Figure 6.
B. This drawing is subject to change without notice.
×
the rise time of the device under the chosen gain setting.
0.65
0.65
DD
Figure 6. Suggested FN Package PCB Layout
and GND) should be bypassed by placing an 0.1-μF capacitor with low ESR and
DD
APPLICATION INFORMATION
1.30
r
power applied second. This means V
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2.90
1.30
r
DD
cannot be applied while the GND
0.40
0.40
1.70
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