PEX8664-16U8DBBRDK PLX [PLX Technology], PEX8664-16U8DBBRDK Datasheet - Page 2

• Manufacturer Part Number: PEX8664-16U8DBBRDK
• Description: PCI Express Gen 2 Switch, 64 Lanes, 16 Ports
• Manufacturer: PLX [PLX Technology]

The PEX 8664 can also be configured in Multi-Host
mode where users can choose up to five ports as
host/upstream ports and assign a desired number of
downstream ports to each host. In Multi-Host mode, a
virtual switch is created for each host port and its
associated downstream ports inside the device. The
traffic between the ports of a virtual switch is completely
isolated from the traffic in other virtual switches. Figure
2 illustrates some configurations of the PEX 8664 in
Multi-Host mode where each ellipse represents a virtual
switch inside the device.
The PEX 8664 also
provides several ways to
configure its registers. The
device can be configured
through strapping pins,
I
software, or an optional
serial EEPROM. This
allows for easy debug
during the development
phase, performance
monitoring during the operation phase, and driver or
software upgrade.
Dual-Host & Failover Support
In Single-Host mode, the
PEX 8664 supports a Non-
Transparent (NT) Port,
which enables the
implementation of dual-
systems for redundancy and
failover capability. The NT
allows systems to isolate
host memory domains by
presenting the
processor subsystem
endpoint rather than
another memory
system. Base address registers are used to translate
addresses; doorbell registers are used to send interrupts
between the address domains; and scratchpad registers
(accessible by both CPUs) allow inter-processor
communication (Figure 3).
Multi-Host & Failover Support
In Multi-Host mode, PEX 8664 can be configured with
up to five upstream host ports, each with its own
dedicated downstream ports. The device can be
configured for 1+1 redundancy or N+1 redundancy. The
© PLX Technology, www.plxtech.com
2
C interface, host
Point
Point
Point
Point
Point
Point
Point
Point
Figure 3. Non-Transparent Port
Figure 3. Non-Transparent Port
End
End
End
End
End
End
End
End
Figure 2. Common Multi-Host Configurations
x8x8x4x4
PEX 8664
PEX 8664
PEX 8664
PEX 8664
Primary Host
Primary Host
Primary Host
Complex
Complex
Complex
Complex
Complex
Complex
Primary Host
Primary Host
Primary Host
x8
PEX 8664
PEX 8664
PEX 8664
PEX 8664
PEX 8664
PEX 8664
PEX 8664
PEX 8664
PEX 8664
PEX 8664
Root
Root
Root
Root
Root
Root
Point
Point
Point
Point
Point
Point
Point
Point
CPU
CPU
CPU
CPU
CPU
CPU
End
End
End
End
End
End
End
End
4 x4s
4 x4s
12 x4s
12 x4s
PEX 8664, PCI Express Gen 2 Switch, 64 Lanes, 16 Ports
x8x8x4x4
x8
NT
NT
Point
Point
Point
Point
Point
Point
Point
Point
End
End
End
End
End
End
End
End
Secondary Host
Secondary Host
Secondary Host
Secondary Host
Secondary Host
Secondary Host
3 x8
Non-Transparent
Non-Transparent
x8
CPU
CPU
CPU
CPU
CPU
CPU
PEX 8664
PEX 8664
PEX 8664
PEX 8664
PEX 8664
PEX 8664
PEX 8664
PEX 8664
PEX 8664
PEX 8664
5 x4s
5 x4s
11 x4s
11 x4s
3 x4
x4
as an
Port
Port
host
host
port
3 x4
x4
Page 2 of 2
PEX 8664 allows the hosts to communicate their status
to each other via special door-bell registers. In failover
mode, if a host fails, the host designated for failover will
disable the upstream port attached to the failing host and
program the downstream ports of that host to its own
domain. Figure 4a shows a two host system in Multi-
Host mode with two virtual switches inside the device
and Figure 4b shows Host 1 disabled after failure and
Host 2 having taken over all of Host 1’s end-points.
Hot Plug for High Availability
Hot plug capability allows users to replace hardware
modules and perform maintenance without powering
down the system. The PEX 8664 hot plug capability
feature makes it suitable for High Availability (HA)
applications. Four downstream ports include a Standard
Hot Plug Controller. If the PEX 8664 is used in an
application where one or more of its downstream ports
connect to PCI Express slots, each port’s Hot Plug
Controller can be used to manage the hot-plug event of
its associated slot. Every port on the PEX 8664 is
equipped with a hot-plug control/status register to
support hot-plug capability through external logic via the
I
SerDes Power and Signal Management
The PEX 8664 supports software control of the SerDes
outputs to allow optimization of power and signal
strength in a system. The PLX SerDes implementation
supports four levels of power – off, low, typical, and
high. The SerDes block also supports loop-back modes
and advanced reporting of error conditions, which
enables efficient management of the entire system.
Interoperability
The PEX 8664 is designed to be fully compliant with the
PCI Express Base Specification r2.0, and is backwards
compatible to PCI Express Base Specification r1.1 and
r1.0a. Additionally, it supports auto-negotiation, lane
reversal, and polarity reversal. Furthermore, the PEX
8664 is tested for Microsoft Vista compliance. All PLX
switches undergo thorough interoperability testing in
PLX’s Interoperability Lab and compliance testing at
the PCI-SIG plug-fest.
2
C interface.
Point
Point
Point
Point
End
End
End
End
Figure 4a. Multi-Host
Host 1
Host 1
Host 1
Host 1
PEX 8664
PEX 8664
Point
Point
Point
Point
End
End
End
End
Point
Point
Point
Point
End
End
End
End
Host 2
Host 2
Host 2
Host 2
Point
Point
Point
Point
End
End
End
End
Figure 4b. Multi-Host Fail-Over
Point
Point
Point
Point
End
End
End
End
Host 1
Host 1
Host 1
Host 1
PEX 8664
PEX 8664
Point
Point
Point
Point
End
End
End
End
5/14/2009, Version 1.1
Point
Point
Point
Point
End
End
End
End
Host 2
Host 2
Host 2
Host 2
Point
Point
Point
Point
End
End
End
End