A3P060-1VQ144T ACTEL [Actel Corporation], A3P060-1VQ144T Datasheet - Page 22

• Manufacturer Part Number: A3P060-1VQ144T
• Description: Automotive ProASIC3 Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Automotive ProASIC3 DC and Switching Characteristics
2 -1 0
Methodology
Total Power Consumption—P
P
P
Total Static Power Consumption—P
N
N
Total Dynamic Power Consumption—P
Global Clock Contribution—P
N
on page
N
page
F
N
P
Sequential Cells Contribution—P
N
sequential cell is used, it should be accounted for as 1.
α
F
Combinatorial Cells Contribution—P
N
α
F
Routing Net Contribution—P
N
N
α
F
I/O Input Buffer Contribution—P
N
α
F
STAT
DYN
CLK
AC1
CLK
CLK
CLK
CLK
INPUTS
OUTPUTS
SPINE
ROW
S-CELL
S-CELL
C-CELL
S-CELL
C-CELL
INPUTS
1
1
1
2
is the toggle rate of VersaTile outputs—guidelines are provided in
is the toggle rate of VersaTile outputs—guidelines are provided in
is the toggle rate of VersaTile outputs—guidelines are provided in
is the I/O buffer toggle rate—guidelines are provided in
P
P
P
P
P
P
P
P
, P
TOTAL
STAT
DYN
CLOCK
S-CELL
C-CELL
NET
INPUTS
is the global clock signal frequency.
is the global clock signal frequency.
is the global clock signal frequency.
is the global clock signal frequency.
is the global clock signal frequency.
is the total dynamic power consumption.
is the total static power consumption.
2-11.
is the number of VersaTile rows used in the design—guidelines are provided in
is the number of global spines used in the user design—guidelines are provided in
AC2
is the number of VersaTiles used as sequential modules in the design.
is the number VersaTiles used as sequential modules in the design.
is the number of VersaTiles used as combinatorial modules in the design.
is the number of VersaTiles used as combinatorial modules in the design.
is the number of VersaTiles used as sequential modules in the design. When a multi-tile
is the number of I/O input buffers used in the design.
= (N
is the number of I/O input buffers used in the design.
= P
= P
2-11.
is the number of I/O output buffers used in the design.
= P
, P
= N
= N
= (P
= N
CLOCK
DC1
S-CELL
AC3
STAT
S-CELL
INPUTS
AC1
C-CELL
+ N
, and P
+ P
+ P
+ N
+ N
INPUTS
* (P
*
*
DYN
S-CELL
C-CELL
SPINE
α
α
AC4
AC5
1
2
* P
/ 2 * P
/ 2 * P
*P
+ P
) *
are device-dependent.
+
DC2
AC2
α
C-CELL
α
1
AC7
AC9
1
+ N
+ N
/ 2 * P
NET
/ 2 * P
CLOCK
TOTAL
* F
* F
OUTPUTS
ROW
+ P
S-CELL
INPUTS
CLK
AC6
CLK
NET
AC8
* P
STAT
) * F
C-CELL
v1.0
+ P
AC3
* P
* F
DYN
INPUTS
CLK
CLK
DC3
+ N
S-CELL
+ P
OUTPUTS
* P
AC4
Table 2-12 on page
) * F
+ P
MEMORY
CLK
Table 2-12 on page
Table 2-12 on page
Table 2-12 on page
+ P
PLL
2-11.
Table 2-12 on
Table 2-12
2-11.
2-11.
2-11.