LFEC6 LATTICE [Lattice Semiconductor], LFEC6 Datasheet - Page 59
![no-image](/images/no-image-200.jpg)
LFEC6
Manufacturer Part Number
LFEC6
Description
LatticeECP/EC Family Data Sheet
Manufacturer
LATTICE [Lattice Semiconductor]
Datasheet
1.LFEC6.pdf
(163 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC6E-3F256C
Manufacturer:
INFINEON
Quantity:
150
Company:
Part Number:
LFEC6E-3F256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Company:
Part Number:
LFEC6E-3F256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Company:
Part Number:
LFEC6E-3F484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Company:
Part Number:
LFEC6E-3F484I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Company:
Part Number:
LFEC6E-3FN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Company:
Part Number:
LFEC6E-3FN484C
Manufacturer:
Lattice
Quantity:
135
Company:
Part Number:
LFEC6E-3QN208C
Manufacturer:
Lattice
Quantity:
456
Company:
Part Number:
LFEC6E-3TN144C
Manufacturer:
LATTICE
Quantity:
450
Lattice Semiconductor
sysCLOCK PLL Timing
f
f
f
f
f
AC Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock.
2. Output clock is valid after t
3. Using LVDS output buffers.
4. Relative to CLKOP.
Timing v.G 0.30
IN
OUT
OUT2
VCO
PFD
DT
PH
OPJIT
SK
W
LOCK
PA
IPJIT
FBKDLY
HI
LO
RST
Parameter
4
2
1
Input Clock Frequency (CLKI, CLKFB)
Output Clock Frequency (CLKOP, CLKOS)
K-Divider Output Frequency (CLKOK)
PLL VCO Frequency
Phase Detector Input Frequency
Output Clock Duty Cycle
Output Phase Accuracy
Output Clock Period Jitter
Input Clock to Output Clock Skew
Output Clock Pulse Width
PLL Lock-in Time
Programmable Delay Unit
Input Clock Period Jitter
External Feedback Delay
Input Clock High Time
Input Clock Low Time
RST Pulse Width
LOCK
Description
for PLL reset and dynamic delay adjustment.
Over Recommended Operating Conditions
Default Duty Cycle
Elected
f
f
90% to 90%
10% to 10%
Divider ratio = integer
At 90% or 10%
OUT
OUT
3-23
>= 100MHz
< 100MHz
Conditions
3
3
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
0.195
Min.
420
100
0.5
0.5
25
25
25
45
10
—
—
—
—
—
—
—
1
Typ.
250
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
+/- 125
+/- 200
+/- 200
Max.
0.05
0.02
420
420
210
840
150
450
55
10
—
—
—
—
—
Units
UIPP
MHz
MHz
MHz
MHz
MHz
ps
ps
ns
µs
ps
ps
ns
ns
ns
ns
UI
%