PT7C4302 PERICOM [Pericom Semiconductor Corporation], PT7C4302 Datasheet - Page 9

• Manufacturer Part Number: PT7C4302
• Description: Real-time Clock Module (3-wire Interface)
• Manufacturer: PERICOM [Pericom Semiconductor Corporation]

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b)
Select whether one diode or two diodes are connected between VCC2 and VCC1.
c)
Select whether one diode or two diodes are connected between VCC2 and VCC1.
Communication
1.
a)
The command byte is shown in Figure 1. Each data transfer is initiated by a command byte. The MSB (Bit 7) must be a logic 1. If
it is 0, writes to the PT7C4302 will be disabled. Bit 6 specifies clock/calendar data if logic 0 or RAM data if logic 1. Bits 1
through 5 specify the designated registers to be input or output, and the LSB (bit 0) specifies a write operation (input) if logic 0 or
read operation (output) if logic 1. The command byte is always input starting with the LSB (bit 0).
b)
All data transfers are initiated by driving the RST input high and terminated by driving the RST input low. A clock cycle is a
sequence of a falling edge followed by a rising edge. For data inputs, data must be valid during the rising edge of the clock and
data bits are output on the falling edge of clock. If the RST input is low all data transfer terminates and the SDA pin goes to a high
impedance state. Data transfer is illustrated in Figure 2 and Figure 3. At power-up, RST must be a logic 0 until VCC > 2.0V. Also
SCLK must be at a logic 0 when RST is driven to a logic 1 state.
PT0225(11/05)
Read/
Read/
Write
Write
DS
RS
Diode Select
Resistor Select
3-wire Interface
Command Byte
RST and SCL Signal
00 or 11
Data
Data
01
10
00
01
10
11
The trickle charger is disabled independently of TCS.
One diode is selected.
Two diodes are selected.
No resistor.
R1 with typ. 2kΩ
R2 with typ. 4kΩ
R3 with typ. 8kΩ
Figure 1 Command byte
9
Real-time Clock Module (3-wire Interface)
Description
Description
Data Sheet
PT7C4302
* Default
* Default
Ver: 0