RT9204AGS RICHTEK [Richtek Technology Corporation], RT9204AGS Datasheet - Page 11

• Manufacturer Part Number: RT9204AGS
• Description: Dual Regulators - Standard Buck PWM DC-DC and Linear Controller
• Manufacturer: RICHTEK [Richtek Technology Corporation]

Input / Output Capacitor
High frequency/long life decoupling capacitors should be
placed as close to the power pins of the load as physically
possible. Be careful not to add inductance to the PCB
trace, as it could eliminate the performance from utilizing
these low inductance components. Consult with the
manuf acturer of the load on specific decoupling
requirements.
The output capacitors are necessary for filtering output
and stabilizing the close loop (see the PWM loop stability).
For powering advanced, high-speed processors, it is
required to meet with the requirement of fast load transient,
high frequency capacitors with low ESR/ESL capacitors
are recommended.
Another concern is high ESR induced ripple may trigger
UV or OV protections.
Linear Regulator Driver
The linear regulator of RT9204/A was designed to drive
bipolar NPN or MOSFET pass transistor. For MOSFET
pass transistor, normally DRV need to provide minimum
V
voltage. When driving MOSFET operating at 5V power
supply system, the gate-drive will be limited at 5V. In this
situation shown in Figure 5, low VT threshold MOSFET
(VT = 1V) and Vout2 setting below 2.5V were suggested.
In V
regulated as higher to 6V providing more gate-drive for
pass MOSFET transistor, V
DS9204/A-08 March 2007
OUT2
VCC = 5V
BOOT
+VT+gate-drive voltage to keep V
= 12V operation condition as Figure 8, VCC is
BOOT
VCC
RT9204/A
DRV
Figure 7
FBL
OUT2
R3
R4
can be set as 3.3V.
R4<1K
OUT2
V
OUT2
as setting
< 2.5V
Preliminary
PWM Loop Stability
The RT9204/A is a voltage mode buck controller designed
for 5V step-down applications. The gain of error amplifier
is fixed at 35dB for simplified design.
The output amplitude of ramp oscillator is 1.6V, the loop
gain and loop pole/zero are calculated as follows:
The RT9204/A Bode plot as shown Figure 9. is stable in
most of application conditions.
V
DC loop gain G = 35 dB
LC filter pole P =
Error Amp pole P = 300kHz
ESR zero Z =
40
30
20
10
BOOT
V
C
L = 2uH
V
V
V
= 12V
OUT
OUT
OUT
OUT
OUT
100
= 3.3V
= 1.5V
= 2.5V
= 3.3V
= 1500uF(33m )
6V
O
BOOT
VCC
O
A
2 ESR C
RT9204/A
1k
A
Loop Gain
2
DRV
1
P
1
Figure 8
Figure 9
O
LC
FBL
= 2.9kHz
10k
Z
1.6
O
5
= 3.2kHz
R3
R4
V
RT9204/A
0.8
OUT
100k
R4<1K
www.richtek.com
V
OUT2
1M
< 3.3V
11